This model shows how to use HDL Coder™ to check, generate, and verify HDL code for a serial input serial output minimum resource HDL FFT model.
To run this example, the DSP System Toolbox™ product is required.
The HDL FFT block used in this model is implemented in the minimum resource architecture. Different from the DSP System Toolbox FFT block, the HDL FFT block requests serial input, generates serial output, and operates at the burst I/O mode. To learn more about the HDL FFT block, refer to the documentation.
The goal of this model is to show how to use the HDL FFT block for HDL code generation.
To open this model, run the following commands
modelname = 'hdlcoderfftdit'; open_system(modelname);
A Pulse Generator block drives the HDL FFT block's start input with a periodic signal in this example. To determine the correct period for this signal, relative to the size of the FFT, the following variables are defined in the example model's initialization function (InitFcn):
N: the FFT length (N=128 for this example)
Tcycle : the total number of clock cycles required by the HDL FFT to complete an N-point FFT. Refer to the documentation for more information
startLen: the period of the Pulse Generator that sends start trigger to the HDL FFT block
The InitFcn is defined in the Callbacks pane of the Simulink Model Explorer.
Using Tcycle to find startLen is one way to specify the period of pulse generator. You may prefer to use your own way to define this parameter.
Data Controller is necessary to buffer the input data considering the two-phase burst I/O feature of this HDL FFT block. The parallel input is saved in a FIFO after serialization and N points of data is read when the Load signal is high. The Load signal is triggered when both start and ready signals are active.
open_system([modelname '/Data Controller']);
The output of the DSP System Toolbox FFT block is stored in a FIFO and is loaded to compare with the results of the HDL FFT block when validated output is generated.
open_system([modelname '/Behavior FFT']);