This example shows how to use Xilinx® System Generator for DSP with HDL Coder™.
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In order to use the Xilinx® System Generator Subsystem block, you must have Xilinx® ISE 13.4 set up with Simulink®.
Using the Xilinx® System Generator Subsystem block enables you to model designs using blocks from both Simulink® and Xilinx®, and to automatically generate integrated HDL code. HDL Coder™ generates HDL code from the Simulink® blocks, and uses Xilinx® System Generator to generate HDL code from the Xilinx® System Generator Subsystem blocks.
In this example, the design, or code generation subsystem, contains two parts: one with Simulink® native blocks, and one with Xilinx® blocks. The Xilinx® blocks are grouped in a Xilinx® System Generator Subsystem (hdlcoder_slsysgen/SLandSysGen/Xilinx System Generator Subsystem). System Generator optimizes these blocks for Xilinx® FPGAs. In the rest of the design, Simulink® blocks and HDL Coder™ offer many model-based design features, such as distributed pipelining and delay balancing, to perform model-level optimizations.
To create a Xilinx® System Generator subsystem:
Put the Xilinx® blocks in one subsystem and set its architecture to "Module" (the default value).
Place a System Generator token at the top level of the subsystem. You can have subsystem hierarchy in a Xilinx® System Generator Subsystem, but there must be a System Generator token at the top level of the hierarchy.
open_system('hdlcoder_slsysgen/SLandSysGen/Xilinx System Generator Subsystem');
In each Xilinx® System Generator subsystem, you must connect input and output ports directly to Gateway In and Gateway Out blocks.
Gateway In blocks must not do non-trivial data type conversion. For example, a Gateway In block can convert between uint8 and UFix_8_0, but changing data sign, word length, or fraction length is not allowed.
In this example, a sum tree is modeled with Simulink® blocks. The distributed pipelining feature can take care of the speed optimization.
Here the Output Pipeline property of hdlcoder_slsysgen/SLandSysGen/Simulink Subsystem is set to "4" and the Distributed Pipelining property is set to "on". Pipeline registers inserted by the distributed pipelining feature will be pushed into the sum tree to reduce the critical path without changing the model function. Other optimizations, such as resource sharing, are also available, but not used in this example.
You can use either makehdl at the command line or HDL Workflow Advisor to generate HDL code. To use makehdl:
You can also generate a testbench, simulate, and synthesize the design as you would for any other model.