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Bit Slicing and Bit Concatenation

This section describes how to use the functions bitsliceget and bitconcat to access and manipulate bit slices (fields) in a fixed-point or integer word. As an example, consider the operation of swapping the upper and lower 4-bit nibbles of an 8-bit byte. The following example accomplishes this task without resorting to traditional mask-and-shift techniques.

function y = fcn(u)
% NIBBLE SWAP 
y = bitconcat( …
      bitsliceget(u, 4, 1), 
      bitsliceget(u, 8, 5));

The bitsliceget and bitconcat functions map directly to slice and concat operators in both VHDL® and Verilog®.

The following listing shows the corresponding generated VHDL code.

ENTITY fcn IS
    PORT (
        clk : IN std_logic; 
        clk_enable : IN std_logic; 
        reset : IN std_logic;
        u : IN std_logic_vector(7 DOWNTO 0);
        y : OUT std_logic_vector(7 DOWNTO 0));
END nibble_swap_7b;


ARCHITECTURE fsm_SFHDL OF fcn IS


BEGIN
    -- NIBBLE SWAP
    y <= u(3 DOWNTO 0) & u(7 DOWNTO 4);
END fsm_SFHDL;

The following listing shows the corresponding generated Verilog code.

module fcn (clk, clk_enable, reset, u, y );
    input clk;
    input clk_enable;
    input reset;
    input [7:0] u;
    output [7:0] y;

    // NIBBLE SWAP
    assign y = {u[3:0], u[7:4]};

endmodule

For more fixed-point bitwise functions you can use in MATLAB® code intended for HDL code generation, see Fixed-Point Bitwise Functions.

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