Generate extra register in HDL code for filter output


'on' (default)

Add an extra output register to the filter's generated HDL code.

The code declares a signal named output_register and includes a PROCESS block similar to the block below. Names and meanings of the timing parameters (clock, clock enable, and reset) and the coding style that checks for clock events may vary depending on other property settings.

Output_Register_Process : PROCESS (clk, reset)
  IF reset = '1' THEN
    output_register <= (OTHERS => '0');
  ELSIF clk'event AND clk = '1' THEN
    IF clk_enable = '1' THEN
      output_register <= output_typeconvert;
    END IF;
END PROCESS Output_Register_Process ;


Omit the extra output register from the filter's generated HDL code.

Consider omitting the extra register if you are incorporating the filter into HDL code that has its own input register. You might also consider omitting the extra register if the latency it introduces to the filter is not tolerable.

Was this topic helpful?