You can specify unique serial, distributed arithmetic, or parallel
architectures for each stage of cascade filters. These options lead
to area efficient implementations of cascade filters, including Digital
Down Converter (DDC), and Digital Up Converter (DUC) objects. You
can use this feature only with the command-line interface (
When you use the Generate HDL dialog box, each stage of a cascade
uses the same architecture options.
You can pass a cell array of values to the
DARadix properties, with each element
corresponding to its respective stage. To skip the corresponding specification
for a stage, specify the default value of that property. When you
set a partition to a size of
-1, the coder implements
a parallel architecture for that stage.
When you create a cascaded filter, Filter Design HDL Coder™ software performs the following actions:
Generates code for each stage as per the inferred architecture.
Generates an timing controller at the top level. This controller then produces clock enables for the module in each stage, which corresponds to the rate and folding factor of that module.