HDL code generation accelerates the development of application-specific integrated circuit (ASIC) and field programmable gate array (FPGA) designs by bridging the gap between system-level design and hardware development.
Traditionally, system designers and hardware developers use hardware description languages (HDLs), such as VHDL and Verilog, to develop hardware filter designs. HDLs provide a proven method for hardware design, but coding filter designs is labor-intensive. Also, algorithms and system-level designs created using HDLs are difficult to analyze, explore, and share. The Filter Design HDL Coder™ workflow automates the implementation of designs in HDL.
First, an architect or designer uses DSP System
Toolbox™ tools (
filterBuilder) to design a filter algorithm targeted for
hardware. Then, a designer uses the Filter Design HDL
Coder tool (
fdhdltool) or command-line interface
generatehdl) to configure code generation options and generate
a VHDL or Verilog implementation of the design. Designers can easily modify these
designs and share them between teams, in HDL or MATLAB® formats.
The generated HDL code adheres to a clean, readable coding style. The optional generated HDL test bench confirms that the generated code behaves as expected, and can accelerate system-level test bench implementation. Designers can also use Filter Design HDL Coder software to generate test signals automatically and validate models against standard reference designs.
This workflow enables designers to fine-tune algorithms and models through rapid prototyping and experimentation, while spending less time on HDL implementation.