Documentation

ClockEnableInputPort

Name HDL port for filter's clock enable input signals

Settings

'string'

The default name for the filter's clock enable input port is clk_enable.

For example, if you specify the string 'filter_clock_enable' for filter entity Hd, the generated entity declaration might look as follows:

ENTITY Hd IS
   PORT( clk                 :  IN  std_logic;
         filter_clock_enable :  IN  std_logic;
         reset               :  IN  std_logic;
         filter_in           :  IN  std_logic_vector (15 DOWNTO 0);
         filter_out          :  OUT std_logic_vector (15 DOWNTO 0);
         );
END Hd;

If you specify a string that is a VHDL or Verilog reserved word, a reserved word postfix string is appended to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd. See ReservedWordPostfix for more information.

Usage Notes

The clock enable signal is asserted active high (1). Thus, the input value must be high for the filter entity's registers to be updated.

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