The Filter Design HDL Coder™ workflow automates the implementation
of filter designs in HDL. First, design a filter, either manually
or by using DSP System Toolbox™ tools Filter Designer or Filter
Builder. Then, use the Generate HDL dialog box or the
generatehdl function to configure code
generation options and generate a VHDL or Verilog implementation of
the design. This workflow enables you to fine-tune algorithms and
models through rapid prototyping and experimentation, while spending
less time on HDL implementation. See Starting Filter Design HDL Coder.
|Fundamental Properties||Customize filter name and input data type, generation language, and target folder|
Access the Filter Design HDL Coder tool.
Select your target language. HDL code is generated in either VHDL or Verilog.
Once your filter design and HDL settings are ready, generate HDL code for your design.
To save your code generation settings, you can generate a script that includes the options you selected.
Save your parameter settings before closing the session.
Design a basic quantized discrete-time FIR filter, generate VHDL code for the filter, and verify the VHDL code with a generated test bench.
Design an IIR filter, generate VHDL code for the filter, and verify the VHDL code with a generated test bench.
HDL code generation accelerates the development of application-specific integrated circuit (ASIC) and field programmable gate array (FPGA) designs by bridging the gap between system-level design and hardware development.