Documentation

Compilation and Simulation Properties

Integrate third-party EDA tools into filter design workflow

Generated scripts help you to compile and simulate the generated code.

The coder generates one script to compile your HDL files and one script to simulate the compiled HDL code. You can modify the commands that the coder prints to the script by setting the properties described on this page. The coder passes the property values to fprintf to create the script. You can use format character vectors supported by the fprintf function. For example, '\n' inserts a newline into the script file.

Specify these properties as Name,Value pair arguments to the generatehdl function, or set the corresponding options in the Generate HDL dialog box.

To see these options in the Generate HDL dialog box, select the EDA Tool Scripts tab, and click Compilation script or Simulation script from the menu in the left column.

Generate Scripts

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Setting this property to 'off' disables generation of compilation, simulation, synthesis, and lint scripts.

Compilation

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For example, if the name of the filter or test bench is my_design, the coder adds the postfix _compile.do to form the name my_design_compile.do.

The implicit argument, %s, is the name of your library, VHDLLibraryName. By default, this property generates the library specification'vlib work/n'. If you compile your filter design with code from other libraries, use VHDLLibraryName to avoid library name conflicts.

This command adds your generated HDL source file to the list of files to be compiled. The coder prints this command to the script once for each generated HDL file. The two arguments are the contents of the SimulatorFlags property (an empty character vector, '', by default) and the file name of the current module.

This command adds your generated HDL source file to the list of files to be compiled. The coder prints this command to the script once for each generated HDL file. The two arguments are the contents of the SimulatorFlags property (an empty character vector, '', by default) and the file name of the current entity.

Specify options that are specific to your application and the simulator you are using. For example, if you must use the 1076–1993 VHDL compiler, specify the flag -93. The coder adds the flags you specify with this option to the compilation command in generated EDA tool scripts. The compilation command is specified by the HDLCompileVHDLCmd or HDLCompileVerilogCmd property.

The coder prints this command to the end of the compilation script. Add commands to this property to customize your script.

Simulation

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For example, if the name of the filter or test bench is my_design, the coder adds the postfix _sim.do to form the name my_design_sim.do.

The coder appends this command to the beginning of the simulation script. Add commands to this property to customize your script.

The two arguments are your library name and top-level module or entity name. If you are using VHDL, you can set the library name in the VHDLLibraryName property. If you are using Verilog, the library name is 'work'. If you compile your filter design with code from other libraries, use VHDLLibraryName to avoid library name conflicts.

The implicit argument is a command that adds the signal paths for the DUT top-level input signals, output signals, and output reference signals.

The coder appends this command to the end of the simulation script. Add commands to this property to customize your script.

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