By default, the coder produces code that includes coefficient multiplier operations. You can optimize these operations such that they decrease the area used and maintain or increase clock speed. You do this by instructing the coder to replace multiplier operations with additions of partial products produced by canonical signed digit (CSD) or factored CSD techniques. These techniques minimize the number of addition operations required for constant multiplication by representing binary numbers with a minimum count of nonzero digits. The amount of optimization you can achieve is dependent on the binary representation of the coefficients used.
Note: The coder does not use coefficient multiplier operations for multirate filters. Therefore, the Coefficient multipliers options described below are disabled for multirate filters.
To optimize coefficient multipliers (for nonmultirate filter types),
the Coefficient multipliers menu in the Filter
architecture pane of the Generate HDL dialog box.
Consider setting an error margin for the generated test bench to account for numeric differences. The error margin is the number of least significant bits the test bench will ignore when comparing the results. To set an error margin,
Select the Test Bench pane in the Generate HDL dialog box. Then click the Configuration tab.
Specify an integer in the Error margin (bits) field that indicates an acceptable minimum number of bits by which the numeric results can differ before the coder issues a warning.
Continue setting other options or click Generate to initiate code generation.
If you are generating code for an FIR filter, see Multiplier Input and Output Pipelining for FIR Filters for information on a related optimization.