By default, the coder produces code that includes coefficient multipliers. You can optimize these operations to decrease the area and maintain or increase clock speed. You can replace multiplier operations with additions of partial products produced by canonical signed digit (CSD) or factored CSD techniques. These techniques minimize the number of addition operations required for constant multiplication by representing binary numbers with a minimum count of nonzero digits. The optimization you can achieve depends on the binary representation of the coefficients used.
Note: The coder does not use coefficient multiplier operations for multirate filters. Therefore, Coefficient multipliers options are disabled for multirate filters.
To optimize coefficient multipliers (for nonmultirate filter types):
the Coefficient multipliers menu in the Filter
architecture pane of the Generate HDL dialog box.
To account for numeric differences, consider setting an error margin for the generated test bench. When comparing the results, the test bench ignores the number of least significant bits specified in the error margin. To set an error margin,
Select the Test Bench pane in the Generate HDL dialog box. Then click the Configuration tab.
Set the Error margin (bits) field to an integer that indicates the maximum acceptable number of bits of difference in the numeric results.
Continue setting other options or click Generate to initiate code generation.
If you are generating code for an FIR filter, see Multiplier Input and Output Pipelining for FIR Filters for information on a related optimization.