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File names and locations, identifiers and comments, ports and resets, HDL language constructs

Properties

BlockGenerateLabel Specify string to append to block labels used for HDL GENERATE statements
CastBeforeSum Enable or disable type casting of input values for addition and subtraction operations
InlineConfigurations Specify whether generated VHDL code includes inline configurations
InstanceGenerateLabel Specify string to append to instance section labels in VHDL GENERATE statements
LoopUnrolling Specify whether VHDL FOR and GENERATE loops are unrolled and omitted from generated VHDL code
OutputGenerateLabel Specify string that labels output assignment block for VHDL GENERATE statements
SafeZeroConcat Specify syntax used in generated VHDL code for concatenated zeros
UseAggregatesForConst Specify whether constants are represented by aggregates, including constants that are less than 32 bits wide
UseRisingEdge Specify VHDL coding style used to check for rising edges when operating on registers
UseVerilogTimescale Allow or exclude use of compiler ˋtimescale directives in generated Verilog code
ClockEnableInputPort Name HDL port for filter's clock enable input signals
ClockInputPort Name HDL port for filter's clock input signals
InputComplex Enable generation ports and signal paths that correspond to filters with complex input data
InputDataType Specify input data type for System objects
InputPort Name HDL port for filter's input signals
InputType Specify HDL data type for filter's input port
OutputPort Name HDL port for filter's output signals
OutputType Specify HDL data type for filter's output port
ResetInputPort Name HDL port for filter's reset input signals
ClockProcessPostfix Specify string to append to HDL clock process names
CoeffPrefix Specify prefix (string) for filter coefficient names
ComplexImagPostfix Specify string to append to imaginary part of complex signal names
ComplexRealPostfix Specify string to append to real part of complex signal names
EntityConflictPostfix Specify string to append to duplicate VHDL entity or Verilog module names
InstancePrefix Specify string prefixed to generated component instance names
PackagePostfix Specify string to append to specified filter name to form name of VHDL package file
ReservedWordPostfix Specify string to append to value names, postfix values, or labels that are VHDL or Verilog reserved words
SplitArchFilePostfix Specify string to append to specified name to form name of file containing filter's VHDL architecture
SplitEntityArch Specify whether generated VHDL entity and architecture code is written to single VHDL file or to separate files
SplitEntityFilePostfix Specify string to append to specified filter name to form name of file that contains filter's VHDL entity
UserComment Specify comment line in header of generated filter and test bench files
VectorPrefix Specify string prefixed to vector names in generated VHDL code
VHDLArchitectureName Specify architecture name for generated VHDL code
VHDLLibraryName Specify target library name used in initialization section of compilation script
Name Specify file name for generated HDL code and for filter VHDL entity or Verilog module
TargetDirectory Identify folder for generated output files
TargetLanguage Specify HDL language to use for generated filter code
VerilogFileExtension Specify file type extension for generated Verilog files
VHDLFileExtension Specify file type extension for generated VHDL files
RemoveResetFrom Suppress generation of resets from shift registers
ResetAssertedLevel Specify asserted (active) level of reset input signal
ResetType Specify whether to use asynchronous or synchronous reset style when generating HDL code for registers
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