Filter Configuration Options

Single rate, multirate, cascaded, other advanced digital filters


AddPipelineRegisters Optimize clock rate used by filter code by adding pipeline registers
AddRatePort Generate rate ports for variable-rate CIC filter
ClockEnableOutputPort For multirate filters (with single clock), specify name of clock enable output port
ClockInputs For multirate filters, specify generation of single or multiple clock inputs
CoefficientMemory Specify type of memory for storage of programmable coefficients for serial FIR filters
CoefficientSource Specify source for FIR or IIR filter coefficients
FracDelayPort Name port for Farrow filter's fractional delay input signal
GenerateHDLTestbench Enable generation of a test bench
SerialPartition Specify number and size of partitions generated for serial filter architectures
TestbenchCoeffStimulus Specify testing options for coefficient memory interface for FIR or IIR filters
TestBenchFracDelayStimulus Specify input stimulus that test bench applies to Farrow filter fractional delay port
TestbenchRateStimulus Specify rate stimulus for CIC filter with rate port
TestBenchStimulus Specify input stimuli that test bench applies to filter
Was this topic helpful?