Filter Configuration Properties

Configure coefficients, complex input ports, and optional ports for specific filter types

Configuration options for filter generation.

The coder provides options to customize your filter. The properties on this page configure specific types of filters, such as those with programmable coefficients or multiple rates. Specify these properties as Name,Value pair arguments to the generatehdl function, or set the corresponding options in the Generate HDL dialog box. These options apply to specific types of filters and are found in various locations in the Generate HDL dialog box.

Filter TypeOptionLocation in Dialog Box
FIR or IIR filter with programmable coefficientsCoefficient source Filter Architecture tab
FIR filter with serial architecture and programmable coefficientsCoefficient memoryGlobal Settings tab, when Coefficient source is set to Processor Interface
Multirate filtersClock inputsGlobal Settings tab
Filters with complex input dataInput complexityGlobal Settings tab > Ports tab.
Single-rate Farrow filterFractional delay portGlobal Settings tab > Ports tab
CIC filterAdd rate portFilter Architecture tab

For filter serialization and pipeline properties, see Optimization Properties.


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When you set this property to 'Internal', the filter coefficients are obtained from the filter object and hard-coded in the generated HDL code.

When you set this property to 'ProcessorInterface', the coder generates a memory interface for the filter coefficients. You can drive this interface with an external microprocessor. The generated entity or module definition for the filter includes these ports for the processor interface:

  • coeffs_in — Input port for coefficient data

  • write_address — The write address for coefficient memory

  • write_enable — The write enable signal for coefficient memory

  • write_done — Signal to indicate completion of coefficient write operation

The generated test bench also generates input stimulus for this interface. See TestBenchCoeffStimulus.

When you use a 'ProcessorInterface' with a serial FIR filter, you can use the CoefficientMemory property to select the type of storage.


This property applies only to FIR filters that have a serial architecture: Fully serial, Partly serial, or Cascade serial.

The default setting, 'Registers', generates code that stores programmable coefficients in a register file. When you set this property to 'SinglePortRAMs' or 'DualPortRAMs', the coder generates the respective RAM interface. See Partly Serial FIR Filter with Programmable Coefficients.

This property applies only when you set CoefficientSource to 'ProcessorInterface'. The coder ignores CoefficientMemory unless it is generating an interface for programmable coefficients.

Optional Ports

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Use this option when your filter design requires complex input data. To enable generation of ports and signal paths for the real and imaginary components of a complex signal, set InputComplex to 'on'.

filt = design(fdesign.lowpass,'equiripple','Filterstructure','dffir','SystemObject',true);
The generated VHDL entity includes ports for both complex data components.
ENTITY firfilt IS
   PORT( clk                :   IN    std_logic; 
         clk_enable         :   IN    std_logic; 
         reset              :   IN    std_logic; 
         filter_in_re       :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
         filter_in_im       :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
         filter_out_re      :   OUT   std_logic_vector(37 DOWNTO 0); -- sfix38_En31
         filter_out_im      :   OUT   std_logic_vector(37 DOWNTO 0)  -- sfix38_En31

END firfilt;
See Using Complex Data and Coefficients.

You can customize the names of the two ports by setting the ComplexRealPostfix and ComplexImagPostfix properties.

When you set this property to 'Single', the coder generates a single clock input for a multirate filter. The module or entity declaration for the filter has a single clock input, an associated clock enable input, and a clock enable output. The generated code includes a counter that controls the timing of data transfers to the filter output (for decimation filters) or input (for interpolation filters). The counter behaves as a secondary clock whose rate is determined by the decimation or interpolation factor. This option provides a self-contained clocking solution for FPGA designs. You can customize the name of the ce_out port using the ClockEnableOutputPort property. Interpolators also pass through the clock enable input signal to an output port named ce_in. This signal indicates when the object accepted an input sample. You can use this signal to control the upstream data flow. You cannot customize this port name.

When you set this property to 'Multiple', the coder generates multiple clock inputs for a multirate filter. The module or entity declaration for the filter has separate clock inputs for each rate of a multirate filter. Each clock input has an associated clock enable input. The coder does not generate a clock enable output. You are responsible for providing input clock signals that correspond to the desired decimation or interpolation factor. To see an example, generate test bench code for your multirate filter and examine the clk_gen processes for each clock. Multiple clock inputs are not supported for:

  • Filters with a Partly serial architecture

  • Multistage sample rate converters: dsp.FIRRateConverter, dsp.FarrowRateConverter, or multirate dsp.FilterCascade

This option provides more flexibility than a single clock input but assumes that you provide higher-level HDL code to drive the input clocks of your filter. The coder does not generate synchronizers between multiple clock domains. See Clock Ports for Multirate Filters and Multirate Filters.

Generate rate and load_rate ports for variable-rate CIC filters. A variable-rate CIC filter has a programmable rate change factor. When the load_rate signal is asserted, the rate port loads in a rate factor. You can generate rate ports for a full-precision filter only.

The generated test bench also includes stimulus for the rate ports. See TestBenchRateStimulus.

The coder assumes that the filter is designed with the maximum rate expected, and that the decimation factor (for CIC decimators) or interpolation factor (for CIC interpolators) is set to this maximum rate-change factor. See Variable Rate CIC Filters.

The fractional delay input of a single-rate Farrow filter enables the use of time-varying delays as the filter operates. The fractional delay input is a signal that ranges from 0 through 1.0. This property specifies the name of this port. For example, if you specify 'frac_delay' for filter entity fdfilt, the coder generates a port with that name.

ENTITY fdfilt IS
   PORT( clk               :  IN  std_logic;
         clk_enable        :  IN  std_logic;
         reset             :  IN  std_logic;
         filter__in        :  IN  std_logic_vector (15 DOWNTO 0); 
         frac_delay        :  IN  std_logic_vector (5 DOWNTO 0);
         filter_out        :  OUT std_logic_vector (15 DOWNTO 0); 
END fdfilt;

Avoiding Reserved Words in Names

If you specify a character vector that is a reserved word in the selected language, the coder appends either:

  • The Reserved word postfix option on the Global Settings > General tab of the Generate HDL dialog box.

  • The ReservedWordPostfix property.

See Setting the Postfix String for Resolving HDL Reserved Word Conflicts.

See Single-Rate Farrow Filters.

The generated test bench also includes stimuli for the rate ports. See TestBenchFracDelayStimulus.

See Also

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