Documentation

generatehdl

Generate HDL code for quantized filter

Syntax

  • generatehdl(Hd,'InputDataType',nt)
    example
  • generatehdl(Hd)
  • generatehdl(___,Name,Value)

Description

example

generatehdl(Hd,'InputDataType',nt) generates HDL code for a filter System object™, Hd, using the default settings. nt is the data type of the input signal, specified as a numerictype object.

  • The function places generated files in a subfolder named hdlsrc, inside your current working folder.

  • The function includes the entity declaration and architecture code in a single source file.

generatehdl(Hd) generates HDL code for a dfilt filter, Hd, using default settings.

generatehdl(___,Name,Value) generates HDL code with additional options specified by one or more Name,Value pair arguments.

Examples

Generate HDL Code for FIR Equiripple Filter

Call fdesign to pass the specifications for designing a minimum order lowpass filter.

d = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2,0.22,1,60)

Those specifications determine the following characteristics for this filter:

  • Normalized passband frequency of 0.2

  • Stopband frequency of 0.22

  • Passband ripple of 1 dB

  • Stopband attenuation of 60 dB

Call the design function to create a FIR equiripple filter, Hd. The function returns a dsp.FIRFilter object.

Hd = design(d,'equiripple','filterstructure','dfsymfir','Systemobject',true)

Call generatehdl to generate VHDL code for the FIR equiripple filter. When the filter is a System object, you must specify the input data type.

generatehdl(Hd,'InputDataType',numerictype(1,16,15),'Name','MyFilter')
### Starting VHDL code generation process for filter: MyFilter
### Generating: H:\hdlsrc\MyFilter.vhd
### Starting generation of MyFilter VHDL entity
### Starting generation of MyFilter VHDL architecture
### Successful completion of VHDL code generation process for filter: MyFilter
### HDL latency is 2 samples 

The function names the file MyFilter.vhd and places it in the default target folder, hdlsrc.

Generate HDL Code and Test Bench for Lowpass Filter

Call fdesign to pass the specifications for designing a minimum order lowpass filter.

d = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2,0.22,1,60)

Call the design function to create a FIR equiripple filter, Hd. The function returns a dsp.FIRFilter object.

Hd = design(d,'equiripple','filterstructure','dfsymfir','Systemobject',true)

Call generatehdl to generate VHDL code and VHDL test bench for the FIR equiripple filter. When the filter is a System object, you must specify the input data type.

generatehdl(Hd,'InputDataType',numerictype(1,16,15),'Name','MyFilter','GenerateHDLTestbench','on','TestBenchName','MyFilterTB')
### Starting VHDL code generation process for filter: MyFilter
### Generating: H:\hdlsrc\MyFilter.vhd
### Starting generation of MyFilter VHDL entity
### Starting generation of MyFilter VHDL architecture
### Successful completion of VHDL code generation process for filter: MyFilter
### HDL latency is 2 samples 
### Starting generation of VHDL Test Bench.
### Generating input stimulus
### Done generating input stimulus; length 4486 samples.
### Generating Test bench: H:\hdlsrc\MyFilterTB.vhd
### Creating stimulus vectors ...
### Done generating VHDL Test Bench.

The function names the files MyFilter.vhd and MyFilterTB.vhd, and places them in the default target folder, hdlsrc.

Fully Parallel FIR Filter with Programmable Coefficients

Generate VHDL code for a direct-form symmetric FIR filter with fully parallel (default) architecture and programmable coefficients. The coder generates a processor interface for the coefficients.

Hd = design(fdesign.lowpass,'equiripple','FilterStructure','dfsymfir')
generatehdl(Hd,'CoefficientSource','ProcessorInterface')

The coder generates this VHDL entity for the filter object Hd.

ENTITY Hd IS
   PORT( clk                   :   IN    std_logic; 
         clk_enable            :   IN    std_logic; 
         reset                 :   IN    std_logic; 
         filter_in             :   IN    real; -- double
         write_enable          :   IN    std_logic; 
         write_done            :   IN    std_logic; 
         write_address         :   IN    real; -- double
         coeffs_in             :   IN    real; -- double
         filter_out            :   OUT   real  -- double
         );

END Hd;

Partly Serial FIR Filter with Programmable Coefficients

Create an asymmetric filter, Hd, and generate VHDL code for the filter. Specify a partly serial architecture. The coder only reacts to CoefficientMemory when you also set CoefficientSource to ProcessorInterface. The generated code includes a dual-port RAM interface for the programmable coefficients.

coeffs = fir1(22,0.45)
Hd = dfilt.dfasymfir(coeffs)
Hd.arithmetic = 'fixed'
generatehdl(Hd,'SerialPartition',[7 4],'CoefficientSource',...
'ProcessorInterface','CoefficientMemory','DualPortRAMs')

Compare Serial Architectures for FIR Filter

Create a direct-form FIR filter.

Hd = design(fdesign.lowpass('N,Fc',8,.4))
Hd.arithmetic = 'fixed'

For comparison, generate a default fully parallel architecture.

generatehdl(Hd,'Name','FullyParallel')
### Starting VHDL code generation process for filter: FullyParallel
### Generating: D:\Work\test\hdlsrc\FullyParallel.vhd
### Starting generation of FullyParallel VHDL entity
### Starting generation of FullyParallel VHDL architecture
### HDL latency is 2 samples
### Successful completion of VHDL code generation process for filter: FullyParallel

Generate a fully serial architecture by setting the partition size to the total filter length. Notice that the system clock rate is nine times the input sample rate. Also, the HDL latency reported is one sample greater than the default parallel implementation.

generatehdl(Hd,'SerialPartition',9,'Name','FullySerial')
### Starting VHDL code generation process for filter: FullySerial
### Generating: D:\Work\test\hdlsrc\FullySerial.vhd
### Starting generation of FullySerial VHDL entity
### Starting generation of FullySerial VHDL architecture
### Clock rate is 9 times the input sample rate for this architecture.
### HDL latency is 3 samples
### Successful completion of VHDL code generation process for filter: FullySerial

Generate a partly serial architecture with three equal partitions. This architecture uses three multipliers. The clock rate is three times the input rate, and the latency is the same as the default parallel implementation.

generatehdl(Hd,'SerialPartition',[3 3 3],'Name','PartlySerial')
### Starting VHDL code generation process for filter: PartlySerial
### Generating: D:\Work\test\hdlsrc\PartlySerial.vhd
### Starting generation of PartlySerial VHDL entity
### Starting generation of PartlySerial VHDL architecture
### Clock rate is 3 times the input sample rate for this architecture.
### HDL latency is 2 samples
### Successful completion of VHDL code generation process for filter: PartlySerial

Generate a cascade-serial architecture by enabling accumulator reuse. Specify the three partitions in descending order of size. Notice that the clock rate is higher than the rate in the partly serial (without accumulator reuse) example.

generatehdl(Hd,'SerialPartition',[4 3 2],'ReuseAccum','on','Name','CascadeSerial')
### Starting VHDL code generation process for filter: CascadeSerial
### Generating: D:\Work\test\hdlsrc\CascadeSerial.vhd
### Starting generation of CascadeSerial VHDL entity
### Starting generation of CascadeSerial VHDL architecture
### Clock rate is 5 times the input sample rate for this architecture.
### HDL latency is 3 samples
### Successful completion of VHDL code generation process for filter: CascadeSerial

You can also generate a cascade-serial architecture without specifying the partitions explicitly. The coder automatically selects partition sizes.

generatehdl(Hd,'ReuseAccum','on', 'Name','CascadeSerial')
### Starting VHDL code generation process for filter: CascadeSerial
### Generating: D:\Work\test\hdlsrc\CascadeSerial.vhd
### Starting generation of CascadeSerial VHDL entity
### Starting generation of CascadeSerial VHDL architecture
### Clock rate is 5 times the input sample rate for this architecture.
### Serial partition # 1 has 4 inputs.
### Serial partition # 2 has 3 inputs.
### Serial partition # 3 has 2 inputs.
### HDL latency is 3 samples
### Successful completion of VHDL code generation process for filter: CascadeSerial

Serial Partitions for Cascaded Filter

Create a two-stage cascade filter and define different serial partitions for each stage. Specify the partition vectors in a cell array.

Hd = design(fdesign.lowpass('N,Fc',8,.4))
Hd.arithmetic = 'fixed'
Hp = design(fdesign.highpass('N,Fc',8,.4))
Hp.arithmetic = 'fixed'
Hc = cascade(Hd,Hp)
generatehdl(Hc,'SerialPartition',{[5 4],[8 1]})

You can only specify different cascade partitions on the command-line. When you specify partitions in the Generate HDL dialog box, all cascade stages use the same partitions.

You can use the hdlfilterserialinfo function to display the effective filter length and partitioning options for each filter stage of a cascade. The function returns a partition vector corresponding to a desired number of multipliers. Request serial partition possibilities for the first stage, and choose a number of multipliers.

hdlfilterserialinfo(Hc.stage(1))
   | Total Coefficients | Zeros | Effective |
   ------------------------------------------
   |          9         |   0   |     9     |

Effective filter length for SerialPartition value is 9.

  Table of 'SerialPartition' values with corresponding values of 
  folding factor and number of multipliers for the given filter.

   | Folding Factor | Multipliers |   SerialPartition   |
   ------------------------------------------------------
   |        1       |      9      |[1 1 1 1 1 1 1 1 1]  |
   |        2       |      5      |[2 2 2 2 1]          |
   |        3       |      3      |[3 3 3]              |
   |        4       |      3      |[4 4 1]              |
   |        5       |      2      |[5 4]                |
   |        6       |      2      |[6 3]                |
   |        7       |      2      |[7 2]                |
   |        8       |      2      |[8 1]                |
   |        9       |      1      |[9]                  |
Select a serial partition vector for a target of two multipliers, and pass the vectors to the generatehdl function. Calling the function this way returns the first possible partition vector, but there are multiple partition vectors that achieve a two-multiplier architecture.
sp1 = hdlfilterserialinfo(Hc.stage(1),'Multiplier',2)
sp2 = hdlfilterserialinfo(Hc.stage(2),'Multiplier',3)
generatehdl(Hc,'serialpartition',{sp1,sp2})
Each stage uses a different clock rate based on the number of multipliers. The coder generates a timing controller to derive these clocks.

Serial Architecture for IIR Filter

Create a direct-form II SOS filter.

Fs = 48e3             % Sampling frequency 
Fc = 10.8e3           % Cut-off frequency 
N = 5                 % Filter Order 
f_lp = fdesign.lowpass('n,f3db',N,Fc,Fs) 
Hd = design(f_lp,'butter','FilterStructure','df1sos') 
Hd.arithmetic = 'fixed'
hdlfilterserialinfo(Hd)

To find possible serial architecture specifications, use the helper function.

hdlfilterserialinfo(Hd)
 Table of folding factors with corresponding number of multipliers for the given filter.

   | Folding Factor | Multipliers |
   --------------------------------
   |        6       |      3      |
   |        9       |      2      |
   |       18       |      1      |
Call generatehdl and request one of the serial architectures by specifying either the NumMultipliers or FoldingFactor property, but not both.
generatehdl(Hd,'NumMultipliers',2)
Alternatively, specify the same architecture with the FoldingFactor property.
generatehdl(Hd,'FoldingFactor',9)
For either of these calls to generatehdl, the coder generates a filter that uses a total of two multipliers, with a latency of nine clock cycles. This architecture uses less area than the parallel implementation, at the expense of latency.

Distributed Arithmetic for Single Rate Filters

Create a direct-form FIR filter and calculate the filter length, FL.

filtdes = fdesign.lowpass('N,Fc,Ap,Ast',30,0.4,0.05,0.03,'linear')
Hd = design(filtdes,'filterstructure','dffir')
Hd.arithmetic = 'fixed'
FL = length(find(Hd.numerator~= 0))
FL =

    31

Specify a set of partitions such that the partition sizes add up to the filter length. This is just one partition option, you can specify other combinations of sizes.

generatehdl(Hd,'DALUTPartition',[8 8 8 7])

Create a direct-form symmetric FIR filter. The filter length is smaller in the symmetric case.

filtdes = fdesign.lowpass('N,Fc,Ap,Ast',30,0.4,0.05,0.03,'linear')
Hd = design(filtdes,'filterstructure','dfsymfir')
Hd.arithmetic = 'fixed'
FL = ceil(length(find(Hd.numerator~= 0))/2)
FL =

    16

Specify a set of partitions such that the partition sizes add up to the filter length. This is just one partition option, you can specify other combinations of sizes.

generatehdl(Hd,'DALUTPartition',[8 8])

    Tip   Use the hdlfilterdainfo function to display the effective filter length, LUT partitioning options, and possible DARadix values for a filter.

Distributed Arithmetic for Multirate Filters

Create a direct-form FIR polyphase decimator, and calculate the filter length, FL.

d = fdesign.decimator(4);
Hm = design(d,'Systemobject',true)
FL = size(polyphase(Hm),2)
FL =

    27

Specify distributed arithmetic LUT partitions that add up to the filter size. When you specify partitions as a vector for a polyphase filter, each subfilter uses the same partitions.

generatehdl(Hm,'InputDataType',numerictype(1,16,15),'DALUTPartition',[8 8 8 3])

You can also specify unique partitions for each subfilter. For the same filter, specify subfilter partitioning as a matrix. The length of the first subfilter is 1, and the other subfilters have length 26.

d = fdesign.decimator(4);
Hm = design(d,'Systemobject',true)
generatehdl(Hm,'InputDataType',numerictype(1,16,15),'DALUTPartition',[1 0 0 0; 8 8 8 2; 8 8 6 4; 8 8 8 2])

    Tip   Use the hdlfilterdainfo function to display the effective filter length, LUT partitioning options, and possible DARadix values for a filter.

Distributed Arithmetic for Cascaded Filters

Create a two-stage cascade filter and define different LUT partitions for each stage. Specify the partition vectors in a cell array.

Hd = design(fdesign.lowpass('N,Fc',8,.4))
Hd.arithmetic = 'fixed'
Hp = design(fdesign.highpass('N,Fc',8,.4))
Hp.arithmetic = 'fixed'
Hc = cascade(Hd,Hp)
generatehdl(Hc,'DALUTPartition',{[5 4],[3 3 3]})

You can also specify different DARadix values for each filter in a cascade. Specify DARadix as a cell array.

generatehdl(Hc,'DALUTPartition',{[5 4],[3 3 3]}, 'DARadix',{2^8,2^4})

You can only specify different cascade partitions on the command-line. When you specify partitions in the Generate HDL dialog box, all cascade stages use the same partitions.

Use the hdlfilterdainfo function to display the effective filter length, LUT partitioning options, and possible DARadix values for each filter stage of a cascade. The function returns a LUT partition vector corresponding to a desired number of address bits. Request LUT partition possibilities for the first stage.

 hdlfilterdainfo(Hc.stage(1))
   | Total Coefficients | Zeros | Effective |
   ------------------------------------------
   |          9         |   0   |     9     |

Effective filter length for SerialPartition value is 9.

  Table of 'DARadix' values with corresponding values of 
  folding factor and multiple for LUT sets for the given filter.

   | Folding Factor | LUT-Sets Multiple | DARadix |
   ------------------------------------------------
   |        1       |         16        |   2^16  |
   |        2       |         8         |   2^8   |
   |        4       |         4         |   2^4   |
   |        8       |         2         |   2^2   |
   |       16       |         1         |   2^1   |

  Details of LUTs with corresponding 'DALUTPartition' values.

   | Max Address Width | Size(bits) |               LUT Details              | DALUTPartition |
   --------------------------------------------------------------------------------------------
   |         9         |    9216    |1x512x18                                |[9]             |
   |         8         |    4628    |1x256x18, 1x2x10                        |[8 1]           |
   |         7         |    2352    |1x128x18, 1x4x12                        |[7 2]           |
   |         6         |    1192    |1x64x17, 1x8x13                         |[6 3]           |
   |         5         |     800    |1x16x16, 1x32x17                        |[5 4]           |
   |         4         |     548    |1x16x16, 1x16x17, 1x2x10                |[4 4 1]         |
   |         3         |     344    |2x8x13, 1x8x17                          |[3 3 3]         |
   |         2         |     252    |1x2x10, 1x4x12, 1x4x13, 1x4x16, 1x4x17  |[2 2 2 2 1]     |

Notes:
1. LUT Details indicates number of LUTs with their sizes. e.g. 1x1024x18
   implies 1 LUT of 1024 18-bit wide locations.

Select address widths and folding factors to obtain LUT partition vectors for each stage.

dp1 = hdlfilterdainfo(Hc.stage(1),'LUTInputs',5,'FoldingFactor',4)
dp2 = hdlfilterdainfo(Hc.stage(2),'LUTInputs',3,'FoldingFactor',4)
generatehdl(Hc,'DALUTPartition',{dp1,dp2})
The first stage uses LUTs with a maximum address size of five bits. The second stage uses LUTs with a maximum address size of three bits. They run at the same clock rate, and have different LUT partitions.

Cascaded Filter with Multiple Architectures

You can specify a mix of serial, distributed arithmetic (DA), and parallel architectures depending upon your hardware constraints. Create a three-stage filter. Each stage is a different type.

h1 = dfilt.dffir([0.05 -.25 .88 0.9 .88 -.25 0.05])
h1.Arithmetic = 'fixed'
h2 = dfilt.dfasymfir([-0.008 0.06 -0.44 0.44 -0.06 0.008])
h2.Arithmetic = 'fixed'
h3 = dfilt.dfsymfir([-0.008 0.06 0.44 0.44 0.06 -0.008])
h3.Arithmetic = 'fixed'
Hd = cascade(h1,h2,h3)

Specify a DA architecture for the first stage, a serial architecture for the second stage, and a fully parallel (default) architecture for the third stage. Set the property values as cell arrays, where each cell applies to a stage. Use the default values —-1 for the partitions and 2 for DARadix— to disable a property for a particular stage.

generatehdl(Hd,'SerialPartition',{-1,3,-1},...
               'DALUTPartition',{[4 3],-1,-1},...
               'DARadix',{2^8,2,2})

Test Bench for FIR Filter with Programmable Coefficients

Create a direct-form symmetric FIR filter with a fully parallel (default) architecture. Define the coefficients for the filter object in the vector b. The coder generates test bench code to test the coefficient interface using a second set of coefficients, c. The coder trims c to the effective length of the filter.

b = [-0.01 0.1 0.8 0.1 -0.01]
c = [-0.03 0.5 0.7 0.5 -0.03]
c = c(1:ceil(length(c)/2))
hd = dfilt.dfsymfir(b)
generatehdl(hd,'GenerateHDLTestbench','on','CoefficientSource','ProcessorInterface',...
'TestbenchCoeffStimulus',c)

IIR Filter with Programmable Coefficients

Generate VHDL code for an SOS IIR Direct Form II filter with programmable coefficients.

Fs = 48e3             % Sampling frequency
Fc = 10.8e3           % Cut-off frequency
N = 5                 % Filter Order
f_lp = fdesign.lowpass('n,f3db',N,Fc,Fs)
Hd = design(f_lp,'butter','FilterStructure','df2sos')
Hd.arithmetic = 'fixed'
Hd.OptimizeScaleValues = 0
generatehdl(Hd,'CoefficientSource','ProcessorInterface')

The coder generates this VHDL entity for the filter object Hd.

ENTITY Hd IS
PORT( clk              :   IN    std_logic; 
      clk_enable       :   IN    std_logic; 
      reset            :   IN    std_logic; 
      filter_in        :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
      write_enable     :   IN    std_logic; 
      write_done       :   IN    std_logic; 
      write_address    :   IN    std_logic_vector(4 DOWNTO 0); -- ufix5
      coeffs_in        :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16
      filter_out       :   OUT   std_logic_vector(15 DOWNTO 0)  -- sfix16_En12
      );

END Hd;

Clock Ports for Multirate Filters

Create a polyphase sample rate converter. By default, the coder generates a single input clock (clk), an input clock enable (clk_enable), and a clock enable output signal named ce_out. The ce_out signal indicates when an output sample is ready. The ce_in output signal indicates when an input sample was accepted. You can use this signal to control the upstream data flow.

frac_cvrter = dsp.FIRRateConverter('InterpolationFactor',5,'DecimationFactor',3)
generatehdl(frac_cvrter,'InputDataType',numerictype(1,16,15))
ENTITY firrc IS
   PORT( clk                             :   IN    std_logic; 
         clk_enable                      :   IN    std_logic; 
         reset                           :   IN    std_logic; 
         filter_in                       :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
         filter_out                      :   OUT   std_logic_vector(35 DOWNTO 0); -- sfix36_En31
         ce_in                           :   OUT   std_logic; 
         ce_out                          :   OUT   std_logic  
         );

END firrc;

You can provide custom names for the input clock enable and the output clock enable signals. You cannot rename the ce_in signal.

frac_cvrter = dsp.FIRRateConverter('InterpolationFactor',5,'DecimationFactor',3)
generatehdl(frac_cvrter,'InputDataType',numerictype(1,16,15),...
            'ClockEnableInputPort','clk_en1','ClockEnableOutputPort','clk_en2')
ENTITY firrc IS
   PORT( clk                             :   IN    std_logic; 
         clk_en1                         :   IN    std_logic; 
         reset                           :   IN    std_logic; 
         filter_in                       :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
         filter_out                      :   OUT   std_logic_vector(35 DOWNTO 0); -- sfix36_En31
         ce_in                           :   OUT   std_logic; 
         clk_en2                         :   OUT   std_logic  
         );

END firrc;

To generate multiple clock input signals for a supported multirate filter, set the ClockInputs property to 'Multiple'. In this case, the coder does not generate any output clock enable ports.

decim = dsp.CICDecimator(7,1,4);
generatehdl(decim,'InputDataType',numerictype(1,16,15),'ClockInputs','Multiple')
ENTITY cicdecimfilt IS
   PORT( clk                             :   IN    std_logic; 
         clk_enable                      :   IN    std_logic; 
         reset                           :   IN    std_logic; 
         filter_in                       :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
         clk1                            :   IN    std_logic; 
         clk_enable1                     :   IN    std_logic; 
         reset1                          :   IN    std_logic; 
         filter_out                      :   OUT   std_logic_vector(27 DOWNTO 0)  -- sfix28_En15
         );

END cicdecimfilt;

Generate Default Altera Quartus II Synthesis Script

Create a filter object. Then call generatehdl, and specify a synthesis tool.

lpf = fdesign.lowpass('fp,fst,ap,ast',0.45,0.55,1,60);
Hd = design(lpf,'equiripple','FilterStructure','dfsymfir','Systemobject',true);
generatehdl(Hd,'InputDataType',numerictype(1,14,13),'HDLSynthTool','Quartus');
The coder generates a script file named firfilt_quartus.tcl, using the default script properties for the Altera® Quartus II synthesis tool.
load_package flow
set top_level firfilt
set src_dir "./hdlsrc"
set prj_dir "q2dir"
file mkdir ../$prj_dir
cd ../$prj_dir
project_new $top_level -revision $top_level -overwrite
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name DEVICE EP2S60F484C3
set_global_assignment -name TOP_LEVEL_ENTITY $top_level
set_global_assignment -name VHDL_FILE "../$src_dir/firfilt.vhd"
execute_flow -compile
project_close

Construct Customized Synthesis Script

This example sets the script automation properties to dummy values to illustrate how the coder constructs the synthesis script from the properties.

lpf = fdesign.lowpass('fp,fst,ap,ast',0.45,0.55,1,60);
Hd = design(lpf,'equiripple','FilterStructure','dfsymfir','Systemobject',true);
generatehdl(Hd,'InputDataType',numerictype(1,14,13),...
'HDLSynthTool','ISE',...
'HDLSynthInit','init line 1 : module name is %s\ninit line 2\n',...
'HDLSynthCmd','command : HDL filename is %s\n',...
'HDLSynthTerm','term line 1\nterm line 2\n');
The coder generates a script file named firfilt_ise.tcl:
init line 1 : module name is firfilt
init line 2
command : HDL filename is firfilt.vhd
term line 1
term line 2

Input Arguments

collapse all

Hd — Filter objectfilter System object, or dfilt object

Filter object for which to generate HDL, for instance, the object returned by the design function. If Hd is a System object, you must specify InputDataType.

Name-Value Pair Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside single quotes (' '). You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

Example: 'TargetLanguage','Verilog'

Data Types

'InputDataType' — Specify input data type for System objectsobject of numerictype class

This argument is required when the input filter, Hd, is a System object. Create this object by calling numerictype(s,w,f), where s is 1 for signed and 0 for unsigned, w is the word length in bits, and f is the number of fractional bits. For more information, see InputDataType.

Language Selection

'TargetLanguage' — Target language'VHDL' (default) | 'Verilog'

For more information, see TargetLanguage.

File Naming and Location

'TargetDirectory' — Output folder'hdlsrc' (default) | string

For more information, see TargetDirectory.

'VerilogFileExtension' — Verilog file extension'.v' (default) | string

For more information, see VerilogFileExtension.

'VHDLFileExtension' — VHDL file extension'.vhd' (default) | string

For more information, see VHDLFileExtension.

Resets

'RemoveResetFrom' — Suppress generation of resets from shift registers 'none' (default) | 'ShiftRegister'

For more information, see RemoveResetFrom.

'ResetAssertedLevel' — Asserted (active) level of reset'active-high' (default) | 'active-low'

For more information, see ResetAssertedLevel.

'ResetType' — Reset type'async' (default) | 'sync'

For more information, see ResetType.

Header Comment and General Naming

'ClockProcessPostfix' — Postfix for clock process names'_process' (default) | string

For more information, see ClockProcessPostfix.

'CoeffPrefix' — Specify prefix (string) for filter coefficient names'coeff' (default) | string

For more information, see CoeffPrefix.

'PackagePostfix' — Postfix for package file name'_pkg' (default) | string

For more information, see PackagePostfix.

'SplitEntityFilePostfix' — Postfix for VHDL entity file names'_entity' (default) | string

For more information, see SplitEntityFilePostfix.

'UserComment' — HDL file header commentstring

For more information, see UserComment.

'VectorPrefix' — Prefix for vector names'vector_of_' (default) | string

For more information, see VectorPrefix.

'VHDLArchitectureName' — VHDL architecture name'rtl' (default) | string

For more information, see VHDLArchitectureName.

'VHDLLibraryName' — VHDL library name'work' (default) | string

For more information, see VHDLLibraryName.

Ports

'InputPort' — Name HDL port for filter input signals 'filter_in' (default) | string

For more information, see InputPort.

'InputType' — Specify HDL data type for filter input port 'std_logic_vector' | 'signed/unsigned' | 'wire' (Verilog)

For more information, see InputType.

'OutputPort' — Name HDL port for filter output signals 'filter_out' (default) | string

For more information, see OutputPort.

'OutputType' — Specify HDL data type for filter output port'Same as input data type' (VHDL default) | 'std_logic_vector' | 'signed/unsigned' | 'wire' (Verilog)

For more information, see OutputType.

'ResetInputPort' — Name HDL port for filter reset input signals'reset' (default) | string

For more information, see ResetInputPort.

Filter Configuration

'CoefficientSource' — Specify source for FIR or IIR filter coefficients'Internal' (default) | 'ProcessorInterface'

For more information, see CoefficientSource.

Advanced Coding

'InlineConfigurations' — Include VHDL configurations'on' (default) | 'off'

For more information, see InlineConfigurations.

'LoopUnrolling' — Unroll VHDL FOR and GENERATE loops'off' (default) | 'on'

For more information, see LoopUnrolling.

'SafeZeroConcat' — Type-safe syntax for concatenated zeros'on' (default) | 'off'

For more information, see SafeZeroConcat.

Optimizations

'CoeffMultipliers' — Specify technique used for processing coefficient multiplier operations'multiplier' (default) | 'csd' | 'factored-csd'

For more information, see CoeffMultipliers.

'DARadix' — Specify number of bits processed simultaneously in distributed arithmetic architecture 2 (default) | N, a nonzero positive integer that is a power of two

For more information, see DARadix.

Test Bench

'GenerateCoSimBlock' — Generate HDL Cosimulation block'off' (default) | 'on'

For more information, see GenerateCosimBlock.

'GenerateCoSimModel' — Generate HDL Cosimulation model'ModelSim' (default) | 'Incisive'

For more information, see GenerateCosimModel.

'TestBenchFracDelayStimulus' — Specify input stimulus that test bench applies to Farrow filter fractional delay port constant (either 'RandSweep' or 'RampSweep') (default) | vector or function returning a vector

For more information, see TestBenchFracDelayStimulus.

'TestBenchStimulus' — Specify input stimuli that test bench applies to filter'impulse' | 'step' | 'ramp' | 'chirp' | 'noise'

For more information, see TestBenchStimulus.

Script Generation

'HDLCompileInit' — Initialization section of compilation script'vlib work\n' (default) | string

For more information, see HDLCompileInit.

'HDLSimInit' — Initialization section of simulation script ['onbreak resume\n',...
'onerror resume\n']
(default) | string

For more information, see HDLSimInit.

'HDLSimTerm' — Termination section of simulation script 'run -all\n' (default) | string

For more information, see HDLSimTerm.

'HDLSimViewWaveCmd' — Waveform viewing command written to simulation script 'add wave sim:%s\n' (default) | string

For more information, see HDLSimViewWaveCmd.

'HDLSynthTool' — Synthesis tool for which the coder generates a script'none' (default) | ‘ISE' | ‘Libero' | 'Precision' | 'Quartus' | 'Synplify' | ‘Vivado' | ‘Custom'

Introduced before R2006a

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