Documentation

generatehdl

Generate HDL code for quantized filter

Syntax

  • generatehdl(Hd)
  • generatehdl(Hd,'InputDataType',nt)
    example
  • generatehdl(Hd,Name,Value)

Description

generatehdl(Hd) generates HDL code for a filter object, Hd, using default settings.

  • The function places generated files in a subfolder named hdlsrc, inside your current working folder.

  • The function includes the VHDL entity and architecture code in a single source file.

example

generatehdl(Hd,'InputDataType',nt) generates HDL code for a filter. Use this syntax when Hd is a System object™. nt is the data type of the input signal, specified as a numerictype object.

generatehdl(Hd,Name,Value) generates HDL code with additional options specified by one or more Name,Value pair arguments.

Examples

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Generate HDL Code for FIR Equiripple Filter

Call fdesign to pass the specifications for designing a minimum order lowpass filter.

d = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2,0.22,1,60)

Those specifications determine the following characteristics for this filter:

  • Normalized passband frequency of 0.2

  • Stopband frequency of 0.22

  • Passband ripple of 1 dB

  • Stopband attenuation of 60 dB

Call the design function to create a FIR equiripple filter object Hd. The function returns a dsp.FIRFilter object.

Hd = design(d,'equiripple','filterstructure','dfsymfir','Systemobject',true)

Call generatehdl to generate VHDL code for the FIR equiripple filter. When the filter is a System object, you must specify the input data type.

generatehdl(Hd,'InputDataType',numerictype(1,16,15),'Name','MyFilter')
### Starting VHDL code generation process for filter: MyFilter
### Generating: H:\hdlsrc\MyFilter.vhd
### Starting generation of MyFilter VHDL entity
### Starting generation of MyFilter VHDL architecture
### Successful completion of VHDL code generation process for filter: MyFilter
### HDL latency is 2 samples 

The function names the file MyFilter.vhd and places it in the default target folder, hdlsrc.

Input Arguments

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Hd — Filter objectfilter object name returned by design

Filter object for which to generate HDL, specified as the name of a filter object that is returned by the design function.

Name-Value Pair Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside single quotes (' '). You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

Example: 'TargetLanguage','Verilog'

Data Types

'InputDataType' — Specify input data type for System objectsobject of numerictype class

Create this object by calling numerictype(s,w,f), where s is 1 for signed and 0 for unsigned, w is the word length in bits, and f is the number of fractional bits. For more information, see InputDataType.

Language Selection

'TargetLanguage' — Target language'VHDL' (default) | 'Verilog'

For more information, see TargetLanguage.

File Naming and Location

'TargetDirectory' — Output directory'hdlsrc' (default) | string

For more information, see TargetDirectory.

'VerilogFileExtension' — Verilog file extension'.v' (default) | string

For more information, see VerilogFileExtension.

'VHDLFileExtension' — VHDL file extension'.vhd' (default) | string

For more information, see VHDLFileExtension.

Resets

'RemoveResetFrom' — Suppress generation of resets from shift registers 'none' (default) | 'ShiftRegister'

For more information, see RemoveResetFrom.

'ResetAssertedLevel' — Asserted (active) level of reset'active-high' (default) | 'active-low'

For more information, see ResetAssertedLevel.

'ResetType' — Reset type'async' (default) | 'sync'

For more information, see ResetType.

Header Comment and General Naming

'ClockProcessPostfix' — Postfix for clock process names'_process' (default) | string

For more information, see ClockProcessPostfix.

'PackagePostfix' — Postfix for package file name'_pkg' (default) | string

For more information, see PackagePostfix.

'SplitEntityFilePostfix' — Postfix for VHDL entity file names'_entity' (default) | string

For more information, see SplitEntityFilePostfix.

'UserComment' — HDL file header commentstring

For more information, see UserComment.

'VectorPrefix' — Prefix for vector names'vector_of_' (default) | string

For more information, see VectorPrefix.

'VHDLArchitectureName' — VHDL architecture name'rtl' (default) | string

For more information, see VHDLArchitectureName.

'VHDLLibraryName' — VHDL library name'work' (default) | string

For more information, see VHDLLibraryName.

Ports

'InputPort' — Name HDL port for filter input signals 'filter_in' (default) | string

For more information, see InputPort.

'InputType' — Specify HDL data type for filter input port 'std_logic_vector' | 'signed/unsigned' | 'wire' (Verilog)

For more information, see InputType.

'OutputPort' — Name HDL port for filter output signals 'filter_out' (default) | string

For more information, see OutputPort.

'OutputType' — Specify HDL data type for filter output port 'Same as input data type' (VHDL default) | 'std_logic_vector' | 'signed/unsigned' | 'wire' (Verilog)

For more information, see OutputType.

'ResetInputPort' — Name HDL port for filter reset input signals'reset' (default) | string

For more information, see ResetInputPort.

Advanced Coding

'CoefficientSource' — Specify source for FIR or IIR filter coefficients'Internal' (default) | 'ProcessorInterface'

For more information, see CoefficientSource.

'InlineConfigurations' — Include VHDL configurations'on' (default) | 'off'

For more information, see InlineConfigurations.

'LoopUnrolling' — Unroll VHDL FOR and GENERATE loops'off' (default) | 'on'

For more information, see LoopUnrolling.

'SafeZeroConcat' — Type-safe syntax for concatenated zeros'on' (default) | 'off'

For more information, see SafeZeroConcat.

Optimizations

'CoeffMultipliers' — Specify technique used for processing coefficient multiplier operations'multiplier' (default) | 'csd' | 'factored-csd'

For more information, see CoeffMultipliers.

'DARadix' — Specify number of bits processed simultaneously in distributed arithmetic architecture 2 (default) | N, a nonzero positive integer that is a power of two

For more information, see DARadix.

Test Bench

'GenerateCoSimBlock' — Generate HDL Cosimulation block'off' (default) | 'on'

For more information, see GenerateCoSimBlock.

'GenerateCoSimModel' — Generate HDL Cosimulation model'ModelSim' (default) | 'Incisive'

For more information, see GenerateCosimModel.

'TestBenchFracDelayStimulus' — Specify input stimulus that test bench applies to Farrow filter fractional delay port constant (either 'RandSweep' or 'RampSweep') (default) | vector or function returning a vector

For more information, see TestBenchFracDelayStimulus.

'TestBenchStimulus' — Specify input stimuli that test bench applies to filter 'impulse' | 'step' | 'ramp' | 'chirp' | 'noise'

For more information, see TestBenchStimulus.

Script Generation

'HDLCompileInit' — Compilation script initialization string'vlib work\n' (default) | string

For more information, see HDLCompileInit.

'HDLCompileTerm' — Compilation script termination string'' (default) | string

For more information, see HDLCompileTerm.

'HDLCompileVerilogCmd' — Verilog compilation command'vlog %s %s\n' (default) | string

For more information, see HDLCompileVerilogCmd.

'HDLCompileVHDLCmd' — VHDL compilation command'vcom %s %s\n' (default) | string

For more information, see HDLCompileVHDLCmd.

'HDLSimCmd' — Specify simulation command written to simulation script 'vsim -novopt %s.%s\n' (default) | string

For more information, see HDLSimCmd.

'HDLSimInit' — Specify string written to initialization section of simulation script ['onbreak resume\n',...
'onerror resume\n']
(default) | string

For more information, see HDLSimInit.

'HDLSynthCmd' — HDL synthesis command'add_file %s\n' (default) | string

For more information, see HDLSynthCmd.

'HDLSynthFilePostfix' — Postfix for synthesis script file namea string that corresponds to the synthesis tool specified by HDLSynthTool. (default) | string

For more information, see HDLSynthFilePostfix.

'HDLSynthInit' — Synthesis script initialization string'project -new %s.prj\n' (default) | string

For more information, see HDLSynthInit.

'HDLSynthTerm' — Synthesis script termination string['set_option -technology VIRTEX4\n',...
'set_option -part XC4VSX35\n',...
'set_option -synthesis_onoff_pragma 0\n',...
'set_option -frequency auto\n',...
'project -run synthesis\n']
(default) | string

For more information, see HDLSynthTerm.

'HDLSynthTool' — Synthesis tool'None' (default) | 'ISE' | 'Precision' | 'Quartus' | 'Synplify'

For more information, see HDLSynthTool.

Introduced before R2006a

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