Documentation

Integration With Third-Party EDA Tools

Generating a Default Script

By default, script generation takes place automatically, as part of the code and test bench generation process. Script files are generated in the target folder.

When HDL code is generated for a filter Hd, the coder writes the following script files:

  • Hd_compile.do: Mentor Graphics® ModelSim® compilation script. This script contains commands to compile the generated filter code, but not to simulate it.

  • Hd_synplify.tcl: Synplify® synthesis script

When test bench code is generated for a filter Hd, the coder writes the following script files:

  • Hd_tb_compile.do: Mentor Graphics ModelSim compilation script. This script contains commands to compile the generated filter and test bench code.

  • Hd_tb_sim.do: Mentor Graphics ModelSim simulation script. This script contains commands to run a simulation of the generated filter and test bench code.

You can enable or disable script generation and customize the names and content of generated script files using either of the following methods:

Structure of Generated Script Files

A generated EDA script consists of three sections, which are generated and executed in the following order:

  1. An initialization (Init) phase. The Init phase performs required setup actions, such as creating a design library or a project file. Some arguments to the Init phase are implicit, for example, the top-level entity or module name.

  2. A command-per-file phase (Cmd). This phase of the script is called iteratively, once per generated HDL file or once per signal. On each call, a different file or signal name is passed in.

  3. A termination phase (Term). This is the final execution phase of the script. One application of this phase is to execute a simulation of HDL code that was compiled in the Cmd phase. The Term phase does not take arguments.

The coder generates scripts by passing format strings to the fprintf function. Using the GUI options (or generatehdl properties) summarized in the following sections, you can pass in customized format strings to the script generator. Some of these format strings take arguments, such as the top-level entity or module name, or the names of the VHDL or Verilog files in the design.

You can use legal fprintf formatting characters. For example, '\n' inserts a newline into the script file.

Customizing Script Generation Using CLI Properties

This section describes how to set properties in the generatehdl function to enable or disable script generation and customize the names and content of generated script files.

Enabling and Disabling Script Generation

The EDAScriptGeneration property controls the generation of script files. By default, EDAScriptGeneration is set 'on'. To disable script generation, set EDAScriptGeneration to 'off', as in the following example.

generatehdl(Hd,'EDAScriptGeneration','off') 

Customizing Script Names

When HDL code is generated, the code generator forms script names by appending a postfix string to the filter name Hd.

When test bench code is generated, the code generator forms script names by appending a postfix string to the test bench name testbench_tb.

The postfix string depends on the type of script (compilation, simulation, or synthesis) being generated. The default postfix strings are shown in the following table. For each type of script, you can define your own postfix using the associated property.

Script TypePropertyDefault Value
Compilation'HDLCompileFilePostfix' '_compile.do'
Simulation'HDLSimFilePostfix' '_sim.do'
Synthesis'HDLSynthFilePostfix' See Automation Scripts for Third-Party Synthesis Tools

The following command generates VHDL code for the filter object myfilt, specifying a custom postfix string for the compilation script. The name of the generated compilation script will be myfilt_test_compilation.do.

generatehdl(myfilt, 'HDLCompileFilePostfix', '_test_compilation.do')

Customizing Script Code

Using the property name/property value pairs summarized in the following table, you can pass in customized format strings to generatehdl . The properties are named according to the following conventions:

  • Properties that apply to the initialization (Init) phase are identified by the substring Init in the property name.

  • Properties that apply to the command-per-file phase (Cmd) are identified by the substring Cmd in the property name.

  • Properties that apply to the termination (Term) phase are identified by the substring Term in the property name.

Property Name and DefaultDescription

Name: 'HDLCompileInit'

Default:'vlib work\n'

Format string passed to fprintf to write the Init section of the compilation script.

Name: 'HDLCompileVHDLCmd'

Default: 'vcom %s %s\n'

Format string passed to fprintf to write the Cmd section of the compilation script for VHDL files. The two arguments are the contents of the 'SimulatorFlags' property and the file name of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default).

Name: 'HDLCompileVerilogCmd'

Default: 'vlog %s %s\n'

Format string passed to fprintf to write the Cmd section of the compilation script for Verilog files. The two arguments are the contents of the 'SimulatorFlags' property and the file name of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default).

Name:'HDLCompileTerm'

Default:''

Format string passed to fprintf to write the termination portion of the compilation script.

Name: 'HDLSimInit'

Default:

 ['onbreak resume\n',...
 'onerror resume\n'] 

Format string passed to fprintf to write the initialization section of the simulation script.

Name: 'HDLSimCmd'

Default: 'vsim -novopt %s.%s\n'

Format string passed to fprintf to write the simulation command. The implicit arguments are replaced with your library name and top-level module or entity name. If you are using VHDL, you can set the library name in VHDLLibraryName. If you are using Verilog it is set to work.

Name: 'HDLSimViewWaveCmd'

Default: 'add wave sim:%s\n'

Format string passed to fprintf to write the simulation script waveform viewing command. The implicit argument adds the signal paths for the DUT top-level input, output, and output reference signals.

Name: 'HDLSimTerm'

Default: 'run -all\n'

Format string passed to fprintf to write the Term portion of the simulation script.

Name: 'HDLSynthInit'

Name: 'HDLSynthCmd'

Name: 'HDLSynthTerm'

These format strings apply to generation of synthesis scripts. See Automation Scripts for Third-Party Synthesis Tools.

generatehdl Example

The following example specifies a Mentor Graphics ModelSim command for the Init phase of a compilation script for VHDL code generated from the filter myfilt.

generatehdl(myfilt, 'HDLCompileInit', 'vlib mydesignlib\n')

The following code shows the resultant script, myfilt_compile.do.

vlib mydesignlib
vcom  myfilt.vhd

Customizing Script Generation with the EDA Tool Scripts Dialog Box

The EDA Tool Scripts dialog box, a subdialog of the Generate HDL dialog box, lets you set the options that control generation of script files. These options correspond to the properties described in Customizing Script Generation Using CLI Properties.

To view and set options in the EDA Tool Scripts dialog box:

  1. Open the Generate HDL dialog box.

  2. Click the EDA Tool Scripts tab in the Generate HDL dialog box.

    The EDA Tool scripts dialog box displays, with the Compilation script options group selected, as shown in the following figure.

  3. The Generate EDA scripts option controls the generation of script files. By default, this option is selected, as shown in the preceding image.

    If you want to disable script generation, clear this option.

  4. The list on the left of the dialog box lets you select from several categories of options. Select a category and set the options as desired. The categories are

Compilation Script Options

The following figure shows the Compilation script pane, with the options set to their default values.

The following table summarizes the Compilation script options.

Option and DefaultDescription

Compile file postfix

'_compile.do'

Postfix string appended to the filter name or test bench name to form the script file name.

Name: Compile initialization

Default:'vlib work\n'

Format string passed to fprintf to write the Init section of the compilation script.

Name: Compile command for VHDL

Default: 'vcom %s %s\n'

Format string passed to fprintf to write the Cmd section of the compilation script for VHDL files. The two arguments are the contents of the Simulator flags option and the file name of the current entity or module. To omit the flags, set Simulator flags to '' (the default). See also Setting Simulator Flags for Compilation Scripts.

Name: Compile command for Verilog

Default: 'vlog %s %s\n'

Format string passed to fprintf to write the Cmd section of the compilation script for Verilog files. The two arguments are the contents of the Simulator flags option and the file name of the current entity or module. To omit the flags, set Simulator flags to '' (the default). See also Setting Simulator Flags for Compilation Scripts.

Name: Compile termination

Default:''

Format string passed to fprintf to write the termination portion of the compilation script.

Setting Simulator Flags for Compilation Scripts.  

You have the option of inserting simulator flags into your generated compilation scripts. For example, you may want to specify a specific compiler version. To specify the flags:

  1. Click Test Bench in the Generate HDL dialog box.

  2. Type the flags of interest in the Simulator flags field. In the following figure, the dialog box specifies that the Mentor Graphics ModelSim simulator use the -93 compiler option for compilation.

Command Line Alternative: Use the generatehdl function's SimulatorFlags property to specify the type of test bench files to be generated.

Simulation Script Options

The following figure shows the Simulation script pane, with the options set to their default values.

The following table summarizes the Simulation script options.

Option and DefaultDescription

Simulation file postfix

'_sim.do'

Postfix string appended to the filter name or test bench name to form the script file name.

Simulation initialization

Default:

 ['onbreak resume\n',...
 'onerror resume\n'] 

Format string passed to fprintf to write the initialization section of the simulation script.

Simulation command

Default: 'vsim -novopt %s.%s\n'

Format string passed to fprintf to write the simulation command. The implicit arguments are replaced with your library name and top-level module or entity name. If you are using VHDL, you can set the library name with VHDLLibraryName. If you are using Verilog it is set to "work".

Simulation waveform viewing command

Default: 'add wave sim:%s\n'

Format string passed to fprintf to write the simulation script waveform viewing command. The implicit argument adds the signal paths for the DUT top-level input, output, and output reference signals.

Simulation termination

Default: 'run -all\n'

Format string passed to fprintf to write the Term portion of the simulation script.

Synthesis Script Options

For information about synthesis script options, see Automation Scripts for Third-Party Synthesis Tools.

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