Specify whether VHDL FOR and GENERATE loops are unrolled and omitted from generated VHDL code



Unroll and omit FOR and GENERATE loops from the generated VHDL code. Verilog is already unrolled.

This option takes into account that some EDA tools do not support GENERATE loops. If you are using such a tool, enable this option to omit loops from your generated VHDL code.

'off' (default)

Include FOR and GENERATE loops in the generated VHDL code.

Usage Notes

The setting of this option does not apply to generated VHDL code during simulation or synthesis.

Was this topic helpful?