Specify whether VHDL
are unrolled and omitted from generated VHDL code
Unroll and omit
from the generated VHDL code. Verilog is already unrolled.
This option takes into account that some EDA tools do not support
If you are using such a tool, enable this option to omit loops from
your generated VHDL code.
in the generated VHDL code.
The setting of this option does not apply to generated VHDL code during simulation or synthesis.