HDL code generation is supported for the following types of multirate filters:
Cascaded Integrator Comb (CIC) interpolation (
Cascaded Integrator Comb (CIC) decimation (
Direct-Form Transposed FIR Polyphase Decimator (
Direct-Form FIR Polyphase Interpolator (
Direct-Form FIR Polyphase Decimator (
Direct-Form FIR Polyphase Sample Rate Converter (
To generate multirate filter code, you must first select and
design one of the supported filter types using FDATool,
or the MATLAB® command line.
After you have created the filter, open the Generate HDL dialog box, set the desired code generation properties, and generate code. GUI options that support multirate filter code generation are described in Code Generation Options for Multirate Filters.
If you prefer to generate code via the
the coder also defines multirate filter code generation properties
that are functionally equivalent to the GUI options. generatehdl Properties for Multirate Filters summarizes
When a multirate filter of a supported type (see Supported Multirate Filter Types) is designed, the enabled/disabled state of several options in the Generate HDL dialog box changes:
The Clock inputs pulldown menu is enabled. This menu provides two alternatives for generating clock inputs for multirate filters.
For multirate filters with the
For CIC filters, the Coefficient multipliers option is disabled. Coefficient multipliers are not used in CIC filters.
However, the Coefficient multipliers option is enabled for Direct-Form Transposed FIR Polyphase Decimator filters.
For CIC filters, the FIR adder style option is disabled, since CIC filters do not require a final adder.
The following figure shows the default settings of the Generate HDL dialog box options for a supported CIC filter.
The Clock inputs options are:
ENTITY declaration for the filter
defines a single clock input with an associated clock enable input
and clock enable output. The generated code maintains a counter that
controls the timing of data transfers to the filter output (for decimation
filters) or input (for interpolation filters). The counter behaves
as a secondary clock enable whose rate is determined by the filter's
decimation or interpolation factor.
Single option is primarily intended
for FPGAs. It provides a self-contained solution for multirate filters,
and does not require you to provide additional code.
A clock enable output is also generated when
selected. If you want to customize the name of this output in generated
code, see Setting the Clock Enable Output Name.
The following code excerpts were generated from a CIC decimation
filter having a decimation factor of
4, with Clock
inputs set to
ENTITY declaration is as follows.
ENTITY cic_decim_4_1_single IS PORT( clk : IN std_logic; clk_enable : IN std_logic; reset : IN std_logic; filter_in : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En15 filter_out : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En15 ce_out : OUT std_logic ); END cic_decim_4_1_single;
counter is maintained by the clock
enable output process (
ce_output). Every 4th clock
counter is toggled to 1.
ce_output : PROCESS (clk, reset) BEGIN IF reset = '1' THEN cur_count <= to_unsigned(0, 4); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN IF cur_count = 3 THEN cur_count <= to_unsigned(0, 4); ELSE cur_count <= cur_count + 1; END IF; END IF; END IF; END PROCESS ce_output; counter <= '1' WHEN cur_count = 1 AND clk_enable = '1' ELSE '0';
The following code excerpt illustrates a typical use of the
in this case to time the filter output.
output_reg_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN output_register <= (OTHERS => '0'); ELSIF clk'event AND clk = '1' THEN IF counter = '1' THEN output_register <= section_out4; END IF; END IF; END PROCESS output_reg_process;
ENTITY declaration for the filter
defines separate clock inputs (each with an associated clock enable
input) for each rate of a multirate filter. (For currently supported
multirate filters, there are two such rates).
The generated code assumes that the clocks are driven at suitable
rates. You are responsible for seeing that the clocks run at relative
rates that correspond to the filter's decimation or interpolation
factor. To see an example of such code, generate test bench code for
your multirate filter and examine the
for each clock.
Multiple option is intended
for ASICs and FPGAs. It provides more flexibility than the
but assumes that you will provide higher-level code for driving your
Note that synchronizers between multiple clock domains are not provided.
Multiple is selected, clock
enable outputs are not generated; therefore the Clock enable
output port field of the Global Settings pane
ENTITY declaration was generated
from a CIC decimation filter with Clock inputs set
ENTITY cic_decim_4_1_multi IS PORT( clk : IN std_logic; clk_enable : IN std_logic; reset : IN std_logic; filter_in : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En15 clk1 : IN std_logic; clk_enable1 : IN std_logic; reset1 : IN std_logic; filter_out : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En15 ); END cic_decim_4_1_multi;
A clock enable output is generated when
selected from the Clock inputs options in the
Generate HDL dialog box. The default name for the clock enable output
To change the name of the clock enable output, enter the desired name into the Clock enable output port field of the Ports pane of the Generate HDL dialog box, as shown in the following figure.
Note that the coder enables the Clock enable output port field only when generating multiple clocks.
If you are using
generatehdl to generate
code for a multirate filter, you can set the following properties
to specify clock generation options: