Documentation

Multirate Filters

Supported Multirate Filter Types

HDL code generation is supported for the following types of multirate filters:

  • Cascaded Integrator Comb (CIC) Interpolator (dsp.CICInterpolator)

  • Cascaded Integrator Comb (CIC) Decimator (dsp.CICDecimator)

  • FIR Polyphase Decimator (dsp.FIRDecimator)

  • FIR Polyphase Interpolator (dsp.FIRInterpolator)

  • FIR Polyphase Sample Rate Converter (dsp.FIRRateConverter)

  • CIC Compensation Interpolator (dsp.CICCompensationInterpolator)

  • CIC Compensation Decimator (dsp.CICCompensationDecimator)

Generating Multirate Filter Code

To generate multirate filter code, first select and design one of the supported filter types using Filter Designer, Filter Builder, or the MATLAB® command line.

After you have created the filter, open the Generate HDL dialog box, set the desired code generation properties, and generate code. See Code Generation Options for Multirate Filters.

To generate code using the generatehdl function, specify multirate filter code generation properties that are functionally equivalent to the GUI options. See generatehdl Properties for Multirate Filters.

Code Generation Options for Multirate Filters

When a multirate filter of a supported type (see Supported Multirate Filter Types) is designed, the enabled/disabled state of several options in the Generate HDL dialog box changes.

  • On the Global settings tab, the Clock inputs pull-down menu is enabled. This menu provides two alternatives for generating clock inputs for multirate filters.

      Note:   The Clock inputs menu is not supported for:

      • Filters with a Partly serial architecture

      • Multistage sample rate converters: dsp.FIRRateConverter, or dsp.FilterCascade containing multiple rates

  • For CIC filters, on the Filter Architecture tab, the Coefficient multipliers option is disabled. Coefficient multipliers are not used in CIC filters.

  • For CIC filters, on the Filter Architecture tab, the FIR adder style option is disabled, since CIC filters do not require a final adder.

The following figure shows the default settings of the Generate HDL dialog box options for a supported CIC filter.

The Clock inputs options are:

  • Single: When you select Single, the coder generates a single clock input for a multirate filter. The module or entity declaration for the filter has a single clock input with an associated clock enable input, and a clock enable output. The generated code includes a counter that controls the timing of data transfers to the filter output (for decimation filters) or input (for interpolation filters). The counter behaves as a secondary clock whose rate is determined by the decimation or interpolation factor. This option provides a self-contained clocking solution for FPGA designs.

    To customize the name of the clock enable output, see Setting the Clock Enable Output Name. Interpolators also pass through the clock enable input signal to an output port named ce_in. This signal indicates when the object accepted an input sample. You can use this signal to control the upstream data flow. You cannot customize this port name.

    The following code excerpts were generated from a CIC decimation filter having a decimation factor of 4, with Clock inputs set to Single.

    The coder generates an input clock, input clock enable, and an output clock enable.

    ENTITY cic_decim_4_1_single IS
       PORT( clk            :   IN    std_logic; 
             clk_enable     :   IN    std_logic; 
             reset          :   IN    std_logic; 
             filter_in      :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
             filter_out     :   OUT   std_logic_vector(15 DOWNTO 0); -- sfix16_En15
             ce_out         :   OUT   std_logic  
             );
    
    END cic_decim_4_1_single;

    The clock enable output process, ce_output, maintains the signal counter. Every 4th clock cycle, counter toggles to 1.

    ce_output : PROCESS (clk, reset)
      BEGIN
        IF reset = '1' THEN
          cur_count <= to_unsigned(0, 4);
        ELSIF clk'event AND clk = '1' THEN
          IF clk_enable = '1' THEN
            IF cur_count = 3 THEN
              cur_count <= to_unsigned(0, 4);
            ELSE
              cur_count <= cur_count + 1;
            END IF;
          END IF;
        END IF; 
      END PROCESS ce_output;
    
      counter <= '1' WHEN cur_count = 1 AND clk_enable = '1' ELSE '0';
    

    The following code excerpt illustrates a typical use of the counter signal, in this case to time the filter output.

    output_reg_process : PROCESS (clk, reset)
      BEGIN
        IF reset = '1' THEN
          output_register <= (OTHERS => '0');
        ELSIF clk'event AND clk = '1' THEN
          IF counter = '1' THEN
            output_register <= section_out4;
          END IF;
        END IF; 
      END PROCESS output_reg_process;
    
  • Multiple: When you select Multiple, the coder generates multiple clock inputs for a multirate filter. The module or entity declaration for the filter has separate clock inputs (each with an associated clock enable input) for each rate of a multirate filter. You are responsible for providing input clock signals that correspond to the desired decimation or interpolation factor. To see an example, generate test bench code for your multirate filter and examine the clk_gen processes for each clock.

    The Multiple option is intended for ASICs and FPGAs. It provides more flexibility than the Single option, but assumes that you provide higher-level HDL code to drive the input clocks of your filter.

    Synchronizers between multiple clock domains are not provided.

    When you select Multiple, the coder does not generate clock enable outputs; therefore the Clock enable output port field of the Global Settings pane is disabled.

    The followingENTITY declaration was generated from a CIC decimation filter with Clock inputs set to Multiple.

    ENTITY cic_decim_4_1_multi IS
       PORT( clk              :   IN    std_logic; 
             clk_enable       :   IN    std_logic; 
             reset            :   IN    std_logic; 
             filter_in        :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
             clk1             :   IN    std_logic; 
             clk_enable1      :   IN    std_logic; 
             reset1           :   IN    std_logic; 
             filter_out       :   OUT   std_logic_vector(15 DOWNTO 0)  -- sfix16_En15
             );
    
    END cic_decim_4_1_multi;
    

Setting the Clock Enable Output Name

The coder generates a clock enable output when you set Clock inputs to Single in the Generate HDL dialog box. The default name for the clock enable output is ce_out.

To change the name of the clock enable output, modify the Clock enable output port field of the Ports pane of the Generate HDL dialog box.

The coder enables the Clock enable output port field only when generating code for a multirate filter with a single input clock.

generatehdl Properties for Multirate Filters

If you are using generatehdl to generate code for a multirate filter, you can set the following properties to specify clock generation options:

  • ClockInputs: Corresponds to the Clock inputs option; selects generation of single or multiple clock inputs for multirate filters.

  • ClockEnableOutputPort: Corresponds to the Clock enable output port field; specifies the name of the clock enable output port.

  • ClockEnableInputPort corresponds to the Clock enable input port field; specifies the name of the clock enable input port.

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