Filter Design HDL Coder™ provides filter optimization options to improve speed or area of the hardware implementation of the generated HDL code. The default filter implementation is a fully parallel architecture with multipliers included. Use these optimizations to modify the implementation of your filter in HDL:
Pipeline registers — See Improving Filter Performance with Pipelining.
Partly or fully serial architecture — See Speed vs. Area Tradeoffs.
Distributed arithmetic (DA) architecture — See Distributed Arithmetic for FIR Filters,
Canonical signed digit (CSD) or factored CSD techniques — See CSD Optimizations for Coefficient Multipliers.
|Optimization Properties||Optimize speed or area of generated HDL code|
How to specify parallel, serial, partly serial, and cascade architectures for filters; optimization tradeoffs resulting from these choices
Using distributed arithmetic to achieve efficient multiply-accumulate circuitry for FIR filters
Describes architecture options for cascaded filters: serial, distributed arithmetic, and parallel
Using canonical signed digit (CSD) or factored CSD techniques to optimize multiplier operations
How to optimize your generated filter code for speed by generating pipeline registers
Global optimization and how to handle numeric differences between optimized HDL code and the original design.
Design an optimized FIR filter, generate Verilog code for the filter, and verify the Verilog code with a generated test bench.