Filter Design HDL Coder™ provides filter optimization options to improve speed or area of the hardware implementation of the generated HDL code. The default filter implementation is a fully parallel architecture with multipliers included. Use these optimizations to modify the implementation of your filter in HDL:
Pipeline registers — See Improving Filter Performance with Pipelining.
Partly or fully serial architecture — See Speed vs. Area Tradeoffs.
Distributed arithmetic (DA) architecture — See Distributed Arithmetic for FIR Filters,
Canonical signed digit (CSD) or factored CSD techniques — See CSD Optimizations for Coefficient Multipliers.
|Optimization Properties||Optimize speed or area of generated HDL code|