Resource usage, clock speed, chip area, latency

Filter Design HDL Coder™ provides filter optimization options to improve speed or area of the hardware implementation of the generated HDL code. The default filter implementation is a fully parallel architecture with multipliers included. Use these optimizations to modify the implementation of your filter in HDL:


hdlfilterdainfo Distributed arithmetic information for filter architectures
hdlfilterserialinfo Serial partition information for filter architectures


Optimization Properties Optimize speed or area of generated HDL code
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