# Documentation

## Polyphase Sample Rate Converters

### About Code Generation for Direct-Form FIR Polyphase Sample Rate Converters

The coder supports code generation for direct-form FIR polyphase sample rate converters (mfilt.firsrc). mfilt.firsrc is a multirate filter structure that combines an interpolation factor and a decimation factor, allowing you to perform fractional interpolation or decimation on an input signal.

The interpolation factor (l) and decimation factor (m) for a polyphase sample rate converter are specified as integers in the RateChangeFactors property of an mfilt.firsrc object. The following example code example constructs an mfilt.firsrc object with a resampling ratio of 5/3:

frac_cvrter = mfilt.firsrc frac_cvrter.RateChangeFactors = [5 3]

Fractional rate resampling can be visualized as a two step process: an interpolation by the factor l , followed by a decimation by the factorm. For example, given a resampling ratio of 5/3, a fractional sample rate converter raises the sample rate by a factor of 5, using a standard five-path polyphase filter. A resampling switch then reduces the new rate by a factor of 3. This process extracts five output samples for every three input samples.

For general information on this filter structure, see the mfilt.firsrc reference page in the DSP System Toolbox™ documentation.

### HDL Implementation for Polyphase Sample Rate Converter

#### Signal Flow, Latency and Timing

The signal flow for the mfilt.firsrc filter is similar to the polyphase FIR interpolator (mfilt.firinterp). The delay line is advanced such that the inputs are delivered after the required set of polyphase coefficients are processed.

The following diagram illustrates the timing of the HDL implementation for mfilt.firsrc . A clock enable input (ce_in) enables the inputs into the filter. The outputs, and a clock enable output (ce_out) are produced and delivered simultaneously, which results in a nonperiodic output.

#### Clock Rate

The clock rate required to process the hardware logic is related to the input rate as:

ceil(Hm.RateChangeFactors(1)/ Hm.RateChangeFactors(2))

For example, for a resampling ratio of 5/3, the clock rate is ceil(5/3) = 2, or twice the input sample rate. The inputs are delivered at every other clock cycle. The outputs are delivered as soon as they are produced and therefore are nonperiodic.

 Note:   When the generated code or hardware logic is deployed, the outputs must be taken into a FIFO designed with outputs occurring at the desired sampling rate.

#### Clock Enable Ports

The generated HDL entity or module the mfilt.firsrc filter has two clock enable ports:

• Clock enable output: the default clock enable output port name is ce_out. As with other multirate filters, you can use the Clock enable output port field of the Generate HDL dialog box to specify the port name. Alternatively, you can use the ClockEnableOutputPort property to set the port name in the generatehdl command.

• Clock enable input: the default clock enable input port name is ce_in. In the current release, there isn't an option to change the name of this port.

#### Test Bench Generation

Generated test benches use the input and output clock enables to force in and verify the test vectors.

#### Generating Code for mfilt.firsrc filters at the Command Line

The following example constructs a fixed-point mfilt.firsrc object with a resampling ratio of 5/3, and generates VHDL filter code.

frac_cvrter = mfilt.firsrc; frac_cvrter.arithmetic = 'fixed'; frac_cvrter.RateChangeFactors = [5 3]; generatehdl(frac_cvrter) 
### Starting VHDL code generation process for filter: frac_cvrter ### Generating: D:\Work\post_2006b_Adsp_sbox\hdlsrc\frac_cvrter.vhd ### Starting generation of frac_cvrter VHDL entity ### Starting generation of frac_cvrter VHDL architecture ### HDL latency is 2 samples ### Successful completion of VHDL code generation process for filter: frac_cvrter 

Filter Design HDL Coder™ does not require special code generation properties when generating code for mfilt.firsrc filters. However, the following code generation options are not supported for mfilt.firsrc filters:

• Use of pipeline registers (AddPipelineRegisters)

• Distributed Arithmetic architecture

• Fully or partially serial architectures

• Multiple clock inputs

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