Documentation

Ports and Identifiers Properties

Customize ports, clocks, resets, identifiers, and comments

Ports and identifier options for filter generation.

Specify these properties as Name,Value pair arguments to the generatehdl function, or set the corresponding options in the Generate HDL dialog box.

Ports, Clocks, and Resets

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For example, generate HDL code for filter object filt, with a custom name for the clock enable signal.

generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
    'ClockEnableInputPort','filter_clk_en');
The generated entity declaration replaces the default port name with your character vector.
ENTITY filt IS
   PORT( clk               :  IN  std_logic;
         filter_clk_en     :  IN  std_logic;
         reset             :  IN  std_logic;
         filter_in         :  IN  std_logic_vector (15 DOWNTO 0); 
         filter_out        :  OUT std_logic_vector (15 DOWNTO 0); 
         );
END filt;

The clock enable signal is asserted active high (1). Thus, drive this port high to activate the registers in the filter.

Avoiding Reserved Words in Names

If you specify a character vector that is a reserved word in the selected language, the coder appends either:

  • The Reserved word postfix option on the Global Settings > General tab of the Generate HDL dialog box.

  • The ReservedWordPostfix property.

See Setting the Postfix String for Resolving HDL Reserved Word Conflicts.

This option is available only when you design a multirate filter and use a single input clock (the default behavior). For example, generate HDL code for filter object filt, with a custom name for the clock enable output port.

filt = dsp.CICDecimator(7,1,4);
generatehdl(filt,'InputDataType',numerictype(1,14,13), ...
    'ClockEnableOutputPort','filter_clk_out');
The generated entity declaration replaces the default port name with your character vector.
ENTITY cicdecimfilt IS
   PORT( clk                             :   IN    std_logic; 
         clk_enable                      :   IN    std_logic; 
         reset                           :   IN    std_logic; 
         filter_in                       :   IN    std_logic_vector(13 DOWNTO 0); -- sfix14_En13
         filter_out                      :   OUT   std_logic_vector(25 DOWNTO 0); -- sfix26_En13
         filter_clk_out                  :   OUT   std_logic  
         );
END cicdecimfilt;
Interpolators also pass through the clock enable input signal to an output port named ce_in. This signal indicates when the object accepted an input sample. You can use this signal to control the upstream data flow. You cannot customize this port name.

Avoiding Reserved Words in Names

If you specify a character vector that is a reserved word in the selected language, the coder appends either:

  • The Reserved word postfix option on the Global Settings > General tab of the Generate HDL dialog box.

  • The ReservedWordPostfix property.

See Setting the Postfix String for Resolving HDL Reserved Word Conflicts.

For example, generate HDL code for filter object filt, with a custom name for the clock input port.

generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
    'ClockInputPort','filter_clk');
The generated entity declaration replaces the default port name with your character vector.
ENTITY filt IS
   PORT( filter_clk        :  IN  std_logic;
         clk_enable        :  IN  std_logic;
         reset             :  IN  std_logic;
         filter_in         :  IN  std_logic_vector (15 DOWNTO 0); 
         filter_out        :  OUT std_logic_vector (15 DOWNTO 0); 
         );
END filt;

Avoiding Reserved Words in Names

If you specify a character vector that is a reserved word in the selected language, the coder appends either:

  • The Reserved word postfix option on the Global Settings > General tab of the Generate HDL dialog box.

  • The ReservedWordPostfix property.

See Setting the Postfix String for Resolving HDL Reserved Word Conflicts.

For example, generate HDL code for filter object filt, with a custom name for the input data port.

generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
   'InputPort','filter_data_in');
The generated entity declaration replaces the default port name with your character vector.
ENTITY filt IS
   PORT( clk               :  IN  std_logic;
         clk_enable        :  IN  std_logic;
         reset             :  IN  std_logic;
         filter_data_in    :  IN  std_logic_vector (15 DOWNTO 0); 
         filter_out        :  OUT std_logic_vector (15 DOWNTO 0); 
         );
END filt;

Avoiding Reserved Words in Names

If you specify a character vector that is a reserved word in the selected language, the coder appends either:

  • The Reserved word postfix option on the Global Settings > General tab of the Generate HDL dialog box.

  • The ReservedWordPostfix property.

See Setting the Postfix String for Resolving HDL Reserved Word Conflicts.

If your target language is VHDL, choose between 'std_logic_vector' and 'signed/unsigned'.

If your target language is Verilog, the input data type is 'wire'.

For example, generate HDL code for filter object filt, with a custom name for the output data port.

generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
    'OutputPort','filter_data_out');
The generated entity declaration replaces the default port name with your character vector.
ENTITY filt IS
   PORT( clk               :  IN  std_logic;
         clk_enable        :  IN  std_logic;
         reset             :  IN  std_logic;
         filter_in         :  IN  std_logic_vector (15 DOWNTO 0); 
         filter_data_out   :  OUT std_logic_vector (15 DOWNTO 0); 
         );
END filt;

Avoiding Reserved Words in Names

If you specify a character vector that is a reserved word in the selected language, the coder appends either:

  • The Reserved word postfix option on the Global Settings > General tab of the Generate HDL dialog box.

  • The ReservedWordPostfix property.

See Setting the Postfix String for Resolving HDL Reserved Word Conflicts.

If your target language is VHDL, choose between 'Same as input data type', 'std_logic_vector', and 'signed/unsigned'.

If your target language is Verilog, the output data type is 'wire'.

For example, generate HDL code for filter object filt, with a custom name for the reset port.

generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
    'ResetInputPort','filter_reset');
The generated entity declaration replaces the default port name with your character vector.

ENTITY filt IS
   PORT( clk               :  IN  std_logic;
         clk_enable        :  IN  std_logic;
         filter_reset      :  IN  std_logic;
         filter_in         :  IN  std_logic_vector (15 DOWNTO 0); 
         filter_out        :  OUT std_logic_vector (15 DOWNTO 0); 
         );
END filt;

To control whether the reset port is active high (drive 1 to reset registers) or active low (drive 0 to reset registers), set the ResetAssertedLevel property.

Avoiding Reserved Words in Names

If you specify a character vector that is a reserved word in the selected language, the coder appends either:

  • The Reserved word postfix option on the Global Settings > General tab of the Generate HDL dialog box.

  • The ReservedWordPostfix property.

See Setting the Postfix String for Resolving HDL Reserved Word Conflicts.

By default, the coder includes reset signals for shift registers in the generated HDL code. Omitting reset signals from shift register code can result in a more efficient FPGA implementation. To disable resets on shift registers, set this property to 'ShiftRegister'. See Suppressing Generation of Reset Logic.

By default, the reset input signal must be driven high (1) to reset registers in the filter design. For example, this code fragment checks whether reset is active high before populating the delay_pipeline register.

Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
  IF reset = '1' THEN
    delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));

When you set this property to 'active-low', the reset input signal must be driven low (0) to reset registers in the filter design. For example, this code fragment checks whether reset is active low before populating the delay_pipeline register.

Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
  IF reset = '0' THEN
    delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));

By default, the coder uses asynchronous resets. The process block does not check for an active clock before performing a reset.

delay_pipeline_process : PROCESS (clk, reset)
BEGIN
  IF Reset_Port = '1' THEN
    delay_pipeline (0 To 50) <= (OTHERS =>(OTHERS => '0'));
  ELSIF Clock_Port'event AND Clock_Port = '1' THEN
    IF ClockEnable_Port = '1' THEN
      delay_pipeline(0) <= signed(Fin_Port);
      delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
    END IF;
  END IF;
END PROCESS delay_pipeline_process;

When you set this property to 'sync', the coder uses a synchronous reset style. In this case, the process block checks for the rising edge of the clock before performing a reset.

delay_pipeline_process : PROCESS (clk, reset)
BEGIN
  IF rising_edge(Clock_Port) THEN
    IF Reset_Port = '0' THEN
     delay_pipeline(0 To 50) <= (OTHERS =>(OTHERS => '0'));
    ELSIF ClockEnable_Port = '1' THEN
     delay_pipeline(0) <= signed(Fin_Port);
     delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
    END IF;
  END IF;
END PROCESS delay_pipeline_process;

Identifiers and Comments

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The coder appends this character vector to the block section labels of VHDL GENERATE statements.

The coder appends this character vector to the instance section labels of VHDL GENERATE statements.

The coder appends this character vector to the output assignment block labels of VHDL GENERATE statements.

The coder uses process blocks to modify the content of the registers in the filter. The label for each of these blocks is derived from a register name and the postfix _process. For example, in the following block declaration, the coder derives the process label from the register name delay_pipeline and the default postfix '_process'.

delay_pipeline_process : PROCESS (clk, reset)
BEGIN

Filter TypeCoefficient Prefix
FIREach coefficient number, starting with 1. For example, the default for the first coefficient is coeff1.
IIRAn underscore (_) and an a or b coefficient name (for example, _a2, _b1, or _b2) followed by _sectionn, where n is the section number. For example, the default for the first numerator coefficient of the third section is coeff_b1_section3.

For example:

ARCHITECTURE rtl OF filt IS
  -- Type Definitions
  TYPE delay_pipeline_type IS ARRAY (NATURAL range <>)
       OF signed(15 DOWNTO 0); -- sfix16_En15
  CONSTANT coeff1 : signed(15 DOWNTO 0) := to_signed(-30, 16); -- sfix16_En15
  CONSTANT coeff2 : signed(15 DOWNTO 0) := to_signed(-89, 16); -- sfix16_En15
  CONSTANT coeff3 : signed(15 DOWNTO 0) := to_signed(-81, 16); -- sfix16_En15
  CONSTANT coeff4 : signed(15 DOWNTO 0) := to_signed(120, 16); -- sfix16_En15

Avoiding Reserved Words in Names

If you specify a character vector that is a reserved word in the selected language, the coder appends either:

  • The Reserved word postfix option on the Global Settings > General tab of the Generate HDL dialog box.

  • The ReservedWordPostfix property.

See Setting the Postfix String for Resolving HDL Reserved Word Conflicts.

The coder appends this character vector to the imaginary part of complex signals in the generated HDL code. See Using Complex Data and Coefficients.

The coder appends this character vector to the real part of complex signals in the generated HDL code. See Using Complex Data and Coefficients.

The coder uses this postfix to resolve duplicate VHDL entity or Verilog module names. For example, if the coder detects two entities with the name MyFilt, the coder names the first entity MyFilt and the second instance MyFilt_block.

The coder prefixes component instance names in the generated HDL code with this character vector.

The coder applies this option only if a package file is required for the design.

For example, if you name your filter mod, the coder adds the postfix _rsvd to form the name mod_rsvd.

By default, the coder writes the generated entity and architecture code to a single file.

When you set this property to 'on', the coder creates the filter VHDL entity and architecture in two separate files. The coder derives the names of the entity and architecture files from the filter name. Postfixes identifying the file as an entity (_entity) or architecture (_arch) are appended to the base file name. To override the default and specify your own postfix, set the SplitArchFilePostfix and SplitEntityFilePostfix properties.

By default, the coder names the architecture file filtername_arch. This option applies when you set the SplitEntityArch property to 'on'.

By default, the coder names the entity file filtername_entity. This option applies when you set the SplitEntityArch property to 'on'.

The coder includes a header comment block at the top of the files it generates. The header comment block contains information about the specifications of the generating filter and about the coder options you selected at the time HDL code was generated.

You can add your own comment lines to the header comment block by setting UserComment to the desired value. The code generator adds leading comment characters that correspond to the target language. When you include new lines or line feeds in the character vector, the coder emits single-line comments for each new line.

For example, this generatehdl command adds two comment lines to the header in the generated VHDL file.

filt = dsp.FIRFilter;
generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
    'UserComment','This is a comment line.\nThis is a second line.')
The resulting header comment block for filter Hlp is:
-- -------------------------------------------------------------
--
-- Module: firfilt
-- Generated by MATLAB(R) 9.1 and the Filter Design HDL Coder 3.1.
-- Generated on: 2016-11-08 15:28:25
-- This is a comment line.
-- This is a second line.
--
-- -------------------------------------------------------------

-- -------------------------------------------------------------
-- HDL Code Generation Options:
--
-- TargetLanguage: VHDL
-- Name: firfilt
-- InputDataType: numerictype(1,16,15)
-- UserComment:  User data, length 47
-- GenerateHDLTestBench: off

-- -------------------------------------------------------------
-- HDL Implementation    : Fully parallel
-- Folding Factor        : 1
-- -------------------------------------------------------------
-- Filter Settings:
--
-- Discrete-Time FIR Filter (real)
-- -------------------------------
-- Filter Structure  : Direct-Form FIR
-- Filter Length     : 2
-- Stable            : Yes
-- Linear Phase      : Yes (Type 2)
-- Arithmetic        : fixed
-- Numerator         : s16,15 -> [-1 1)
-- -------------------------------------------------------------

The coder prefixes the names of vector signals in the VHDL code with this character vector. This property does not apply to generated Verilog code.

See Also

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