Documentation

ResetInputPort

Name HDL port for filter's reset input signals

Settings

'string'

The default name for the filter's reset input port is reset.

For example, if you specify the string 'filter_reset' for filter entity Hd, the generated entity declaration might look as follows:

ENTITY Hd IS
   PORT( clk               :  IN  std_logic;
         clk_enable        :  IN  std_logic;
         filter_reset      :  IN  std_logic;
         filter_in         :  IN  std_logic_vector (15 DOWNTO 0); 
         filter_out        :  OUT std_logic_vector (15 DOWNTO 0); 
         );
END Hd;

If you specify a string that is a VHDL reserved word, a reserved word postfix string is appended to form a valid VHDL identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd. See ReservedWordPostfix for more information.

Usage Notes

If the reset asserted level is set to active high, the reset input signal is asserted active high (1) and the input value must be high (1) for the entity's registers to be reset. If the reset asserted level is set to active low, the reset input signal is asserted active low (0) and the input value must be low (0) for the entity's registers to be reset.

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