Documentation

ResetType

Specify whether to use asynchronous or synchronous reset style when generating HDL code for registers

Settings

'async' (default)

Use an asynchronous reset style. The following generated code fragment illustrates the use of asynchronous resets. Note that the process block does not check for an active clock before performing a reset.

delay_pipeline_process : PROCESS (clk, reset)
BEGIN
  IF Reset_Port = '1' THEN
    delay_pipeline (0 To 50) <= (OTHERS =>(OTHERS => '0'));
  ELSIF Clock_Port'event AND Clock_Port = '1' THEN
    IF ClockEnable_Port = '1' THEN
      delay_pipeline(0) <= signed(Fin_Port)
      delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
    END IF;
  END IF;
END PROCESS delay_pipeline_process;

'sync'

Use a synchronous reset style. Code for a synchronous reset follows. This process block checks for a clock event, the rising edge, before performing a reset.

delay_pipeline_process : PROCESS (clk, reset)
BEGIN
  IF rising_edge(Clock_Port) THEN
    IF Reset_Port = '0' THEN
     delay_pipeline(0 To 50) <= (OTHERS =>(OTHERS => '0'));
    ELSIF ClockEnable_Port = '1' THEN
     delay_pipeline(0) <= signed(Fin_Port)
     delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
    END IF;
  END IF;
END PROCESS delay_pipeline_process;
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