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Test Bench Properties

Enable and customize generated test bench

Generate HDL test bench to use in conjunction with the generated HDL code.

The coder can optionally generate an HDL test bench that applies generated input stimuli to the HDL code generated for the filter. The test bench compares the output of the HDL filter with saved result vectors from MATLAB® simulation. You can configure clocks, resets, input stimuli, and other test bench options using the properties on this page. Specify these properties as Name,Value pair arguments to the generatehdl function, or set the corresponding options on the Test Bench tab in the Generate HDL dialog box.

General

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When you set this property to 'on', the coder generates a test bench for your HDL filter code. The test bench applies generated input stimuli to the HDL code generated for the filter. The test bench compares the output of the HDL filter with saved result vectors from MATLAB simulation. Configure the clock and reset behavior, input stimulus, and other test bench features using the properties on this page.

Note

The generatetb function was removed in R2011a. Instead, call generatehdl and set the GenerateHDLTestbench property to 'on'.

This name is also used for the VHDL entity or Verilog module. The coder creates the file in the location specified in the TargetDirectory property. The coder uses the file type extension defined by the VerilogFileExtension or VHDLFileExtension property.

Avoiding Reserved Words in Names

If you specify a character vector that is a reserved word in the selected language, the coder appends either:

  • The Reserved word postfix option on the Global Settings > General tab of the Generate HDL dialog box.

  • The ReservedWordPostfix property.

See Setting the Postfix String for Resolving HDL Reserved Word Conflicts.

Some HDL optimizations can generate test bench code that produces numeric results that differ from the results produced by the original filter function. Such optimizations include:

The error margin specifies an acceptable minimum number of bits by which the numeric results can differ before the test bench issues a warning.

When you set this property to 'on', the coder writes separate files for test bench code, helper functions, and test bench data. The file names are derived from the TestBenchName and TestBenchDataPostFix properties. For example, if the test bench name is my_fir_filt, the default test bench file names are:

  • my_fir_filt_tb — Test bench code

  • my_fir_filt_tb_pkg — Helper functions package

  • my_fir_filt_tb_data — Test vector data package

The coder uses the file type extension defined by the VerilogFileExtension or VHDLFileExtension property.

When you set this property to 'off', the coder writes a single test bench file containing HDL test bench code, helper functions, and test bench data.

This property applies when you set MultifileTestBench to 'on'. If the name of your test bench is test_fir_tb, the coder adds the postfix _data to form the test bench data file name test_fir_tb_data.

This property applies when you set MultifileTestBench to 'on'. The generated test bench represents reference signal data as arrays. The test bench stores the reference signal values in the _data file.

CONSTANT filter_out_expected : filter_in_data_log_type :=
    (
         -2.4228738523269194E-03,
         -2.0832449820793104E-03,
         6.7703446401186345E-03,...
Then the test bench accesses one array value at a time for comparison. This postfix applies to the output signal in the _tb file.
 SIGNAL filter_out_ref                   : real := 0.0; -- double
...
 filter_out_ref <= filter_out_expected(TO_INTEGER(filter_out_addr));

Clocks and Resets

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You can specify an integer or a double-precision floating-point value (with a maximum of 6 significant digits after the decimal point). This option applies only if ForceClock is set to 'on'.

You can specify an integer or a double-precision floating-point value (with a maximum of 6 significant digits after the decimal point). This option applies only if ForceClock is set to 'on'.

When you set this property to 'on', the test bench forces the clock input signals. When this option is set, the values of the ClockHighTime and ClockLowTime properties control the clock waveform.

When you set this property to 'off', you must drive the clock input signals from a user-defined external source.

When you set this property to 'on', the test bench forces the clock enable input signals. The polarity is active high (1). This signal also obeys the setting of the HoldTime property.

When you set this property to 'off', you must drive the clock enable input signals from a user-defined external source.

The test bench waits this number of cycles between deasserting the reset signal and asserting the clock enable signal. The HoldTime property also applies.

In the figure, the test bench deasserts an active-high reset signal after the interval labeled Hold Time. The test bench then asserts clock enable after a further interval, labeled Clock enable delay.

When you set this property to 'on', the test bench forces the reset input signals. You can also specify a hold time to control the timing of reset by setting the HoldTime property.

When you set this property to 'off', you must drive the reset input signals from a user-defined external source.

The test bench holds filter data input signals and forced reset input signals for this number of nanoseconds (ns) past the rising clock edge. You can specify an integer or a double-precision floating-point value (with a maximum of 6 significant digits after the decimal point). This option applies to reset input signals only if ForceReset is set to 'on'.

The hold time is the amount of time that reset input signals and input data are held past the clock rising edge. The following figures show the application of a hold time, thold, for reset and data input signals when the signals are forced to active high and active low. The ResetLength property is set to its default of 2 cycles, and the test bench asserts the reset signal for a total of 2 cycles plus thold.

Hold Time for Reset Input Signals

Hold Time for Data Input Signals

The figure shows the default case. The test bench asserts an active-high reset signal for 2 clock cycles.

Serial architectures and distributed arithmetic architectures implement internal clock rates higher than the input rate. In such filter implementations, the base clock runs N cycles (N >= 2) for each input sample. This property specifies the number of clock cycles that the test bench holds each input data value in a valid state.

  • When you set this property to 'on', the generated test bench code holds input data values in a valid state across N clock cycles.

  • When you set this property to 'off', the generated test bench code holds data values in a valid state for only one clock cycle. For the next N-1 cycles, data is in an unknown state (expressed as 'X'). Forcing the input data to an unknown state verifies that the generated filter code registers the input data only on the first cycle.

When you set this property to 'on', the test bench drives zeros to the input ports at the start of the simulation.

When you set this property to 'off', the test bench drives an unknown state (expressed as 'X') to the input ports at the start of the simulation.

Stimulus

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The coder chooses a default set of stimuli depending on your filter type. The default set is {'impulse','step','ramp','chirp','noise'}. For IIR filters, 'impulse' and 'step' are excluded. You can specify combinations of stimuli as character vectors in a cell array, in any order. For example:

generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
    'GenerateHDLTestbench','on', ...
    'TestBenchStimulus',{'ramp','impulse','noise'})
You can specify a custom input vector using the TestBenchUserStimulus property. When TestBenchUserStimulus is a nonempty vector, it takes priority over TestBenchStimulus.

When this property is set to a non-empty vector, the generated test bench applies this input stimulus to your filter. Otherwise, the test bench uses the TestBenchStimulus property to generate input data.

For example, this function call generates a square wave with a sample frequency of 8 bits per second (Fs/8).

repmat([1 1 1 1 0 0 0 0],1,10)
Specify this stimulus when you call generatehdl.
generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
   'GenerateHDLTestbench','on', ...
   'TestBenchUserStimulus',repmat([1 1 1 1 0 0 0 0],1,10))

This property applies when you set CoefficientSource to 'ProcessorInterface'.

  • [] — The test bench loads the coefficients from the filter object and then forces the input stimuli. This sequence shows the response to the input stimuli and verifies that the interface writes one set of coefficients into the RAM as expected.

  • FIR filter — Specify a vector of coefficient values. The filter processes the input stimuli twice. First, the test bench loads the coefficients from the filter object and forces the input stimuli to show the response. Then, the filter loads the coefficients specified by TestBenchCoeffStimulus, and processes the same input stimuli for a second time. In this case, the internal states of the filter, as set by the first run of the input stimulus, are retained. The test bench verifies that the interface writes two different sets of coefficients into the RAM. See Programmable Filter Coefficients for FIR Filters and Test Bench for FIR Filter with Programmable Coefficients.

  • IIR filter — Specify a cell array containing a column vector of scale values, and a second-order section (SOS) matrix for the filter. The test bench verifies that the interface writes two different sets of coefficients into the RAM, in the same way as an FIR filter. See Programmable Filter Coefficients for IIR Filters.

This property applies when generating a test bench for a single-rate Farrow filter. By default, the test bench drives the fractional delay input signal with a constant value obtained from the filter object. You can specify this input stimulus as a vector, a function returning a vector, or choose one of two predefined options:

'RandSweep' — A vector of values incrementally increasing over the range from 0 to 1. This stimulus signal has the same duration as the input signal to the filter, but changes at a slower rate. Each fractional delay value obtained from the vector is held for 10% of the total duration of the input signal.

'RampSweep' — A vector of random values from 0 through 1. This stimulus signal has the same duration as the filter’s input signal, but changes at a slower rate. Each fractional delay value obtained from the vector is held for 10% of the total duration of the input signal.

See Single-Rate Farrow Filters.

This property applies for variable-rate CIC filters, when you set AddRatePort to 'on'. If you do not specify TestBenchRateStimulus, the coder uses the maximum rate-change factor specified in the filter object.

See Variable Rate CIC Filters.

Cosimulation

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When you set this property to 'on', the coder generates and opens a Simulink model that contains an HDL Cosimulation block for each of Mentor Graphics® ModelSim® and Cadence Incisive®. This feature requires an HDL Verifier™ license.

The coder configures the generated HDL Cosimulation blocks to conform to the port and data type interface of the filter selected for code generation. To cosimulate your design with the desired HDL simulator, copy the block corresponding to your HDL simulator into a Simulink model in place of the corresponding filter block.

When you set this property to 'ModelSim' or 'Incisive', the coder generates and opens a Simulink model that contains an HDL cosimulation block for the selected simulator, and a behavioral implementation of the filter design. The model applies generated input stimuli, and compares the output of the EDA simulator with the output of the behavioral filter subsystem. This feature requires an HDL Verifier license.

You can customize the input stimulus and error margin using the same properties as you would for the generated HDL test bench.

See Generating a Simulink Model for Cosimulation with an HDL Simulator.

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