Documentation

TestBenchName

Name VHDL test bench entity or Verilog module and file that contains test bench code

Settings

'string'

The file type extension depends on the type of test bench that is being generated:

  • For Verilog files, the extension is defined by the Verilog file extension option.

  • For VHDL files, the extension is defined by the VHDL file extension option.

The file is placed in the target folder.

If you specify a string that is a VHDL or Verilog reserved word, a reserved word postfix string is appended to form a valid HDL identifier. For example, if you specify the reserved word entity, the resulting name string would be entity_rsvd. To set the reserved word postfix string, see ReservedWordPostfix.

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