Documentation

Testing with an HDL Test Bench

Workflow for Testing With an HDL Test Bench

Generating the Filter and Test Bench HDL Code

Use the Filter Design HDL Coder™ GUI or command line interface to generate the HDL code for your filter design and test bench. As explained in Specifying a Test Bench Type, the GUI generates a VHDL or Verilog test bench file by default, depending on your language selection. To specify a language-specific test bench type explicitly, select the Test bench language option in the Test Bench pane of the Generate HDL dialog box.

The following figure shows settings for generating the filter (VHDL) and test bench (Verilog) files MyFilter.vhd, and MyFilter_tb.v. The dialog box also specifies that the generated files are to be placed in the default target folder hdlsrc under the current working folder.

After you click Generate, the coder displays progress information similar to the following in the MATLAB® Command Window:

### Starting VHDL code generation process for filter: MyFilter
### Generating: C:\Work\sl_hdlcoder_work\hdlsrc\MyFilter.vhd
### Starting generation of MyFilter VHDL entity
### Starting generation of MyFilter VHDL architecture
### HDL latency is 2 samples
### Successful completion of VHDL code generation process for filter: MyFilter

### Starting generation of VERILOG Test Bench
### Generating input stimulus
### Done generating input stimulus; length 3429 samples.
### Generating Test bench: C:\Work\sl_hdlcoder_work\hdlsrc\MyFilter_tb.v
### Please wait ...
### Done generating VERILOG Test Bench

    Note:   The length of the input stimulus samples varies from filter to filter. For example, the value 3429 in the preceding message sequence is not fixed; the value is dependent on the filter under test.

If you call the generatehdl function from the command line interface, you must

  • Specify 'VHDL' or 'Verilog' for the TbType parameter.

  • For double-precision filters, you must specify the type that matches the target language specified for your filter code.

  • You can use the function generatetbstimulus to return the test bench stimulus to the MATLAB Command Window.

See generatehdl function reference for details on the property name and property value pairs that you can specify for customizing the output.

Starting the Simulator

After you generate your filter and test bench HDL files, start your simulator. When you start the Mentor Graphics® ModelSim® simulator, a screen display similar to the following appears:

After starting the simulator, set the current folder to the folder that contains your generated HDL files.

Compiling the Generated Filter and Test Bench Files

Using your choice HDL compiler, compile the generated filter and test bench HDL files. Depending on the language of the generated test bench and the simulator you are using, you may have to complete some precompilation setup. For example, in the Mentor Graphics ModelSim simulator, you might choose to create a design library to store compiled VHDL entities, packages, architectures, and configurations.

The following Mentor Graphics ModelSim command sequence changes the current folder to hdlsrc, creates the design library work, and compiles VHDL filter and filter test bench code. The vlib command creates the design library work and the vcom commands initiate the compilations.

cd hdlsrc
vlib work
vcom MyFilter.vhd
vcom MyFilter_tb.vhd

    Note:   For VHDL test bench code that has floating-point (double) realizations, use a compiler that supports VHDL-93 or VHDL-02 (for example, in the Mentor Graphics ModelSim simulator, specify the vcom command with the -93 option). Do not compile the generated test bench code with a VHDL-87 compiler. VHDL test benches using double- precision data types do not support VHDL-87, because test bench code uses the image attribute, which is available only in VHDL-93 or higher.

The following screen display shows this command sequence and informational messages displayed during compilation.

Running the Test Bench Simulation

Once your generated HDL files are compiled, load and run the test bench. The procedure for doing this varies depending on the simulator you are using. In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the vsim command. For example:

vsim work.MyFilter_tb

The following display shows the results of loading work.MyFilter_tb with the vsim command.

Once the design is loaded into the simulator, consider opening a display window for monitoring the simulation as the test bench runs. For example, in the Mentor Graphics ModelSim simulator, you might use the add wave * command to open a wave window to view the results of the simulation as HDL waveforms.

To start running the simulation, issue the start simulator command. For example, in the Mentor Graphics ModelSim simulator, you can start a simulation with the run -all command.

The following display shows the add wave * command being used to open a wave window and the -run all command being used to start a simulation.

As your test bench simulation runs, watch for error messages. If error messages appear, you must interpret them as they pertain to your filter design and the code generation options you applied. For example, a number of HDL customization options allow you to specify settings that can produce numeric results that differ from those produced by the original filter object. For HDL test benches, expected and actual results are compared. If they differ (excluding the specified error margin), an error message similar to the following is returned:

Error in filter test: Expected xxxxxxxx Actual xxxxxxxx

You must determine whether the actual results are expected based on the customizations you specified when generating the filter HDL code.

    Note:   The failure message that appears in the preceding display is not flagging an error. If the message includes the string Test Complete, the test bench has run to completion without encountering an error. The Failure part of the message is tied to the mechanism the coder uses to end the simulation.

The following wave window shows the simulation results as HDL waveforms.

Enabling Test Bench Generation

To enable generation of an HDL test bench:

  1. Select the Test Bench pane in the Generate HDL dialog box.

  2. Select the HDL test bench option, as shown in the following figure.

  3. Click Generate to generate HDL and test bench code.

    Tip   By default, HDL test bench is selected.

Command Line Alternative: Use the generatehdl function with the property GenerateHDLTestbench to generate an HDL test bench.

Renaming the Test Bench

The coder derives the name of the test bench file from the name of the quantized filter for which the HDL code is being generated and the postfix _tb. The file type extension depends on the type of test bench that is being generated.

If the Test Bench Is a...The Extension Is...
Verilog fileDefined by the Verilog file extension field in the General subpane of the Global Settings pane of the Generate HDL dialog box
VHDL fileDefined by the VHDL file extension field in the Global Settings pane of the Generate HDL dialog box

The file is placed in the folder defined by the Folder option in the Target pane of the Generate HDL dialog box.

To specify a test bench name, enter the name in the Name field of the Test bench settings pane, as shown in the following figure.

    Note:   If you enter a string that is a VHDL or Verilog reserved word, the coder appends the reserved word postfix to the string to form a valid identifier.

Command Line Alternative: Use the TestBenchName to property to specify a name for your filter's test bench.

Specifying a Test Bench Type

Specifying a Test Bench Type

The coder can generate two types of test benches:

  • A VHDL file that you can simulate in a simulator of choice

  • A Verilog file that you can simulate in a simulator of choice

By default, the coder produces a VHDL or Verilog file, depending on your Language selection. Use the Test bench language pulldown menu in the Test bench generate output panel of the Generate HDL dialog box. to select a test bench language that differs from the Language selection. In the following figure, the Language is VHDL, while the Test bench language is Verilog.

Command Line Alternative: Use the TbType parameter to specify the type of test bench files to be generated.

Splitting Test Bench Code and Data into Separate Files

By default, the coder generates a single test bench file, containing test bench helper functions, data, and test bench code. You can split these elements into separate files by selecting the Multi-file test bench option in the Configuration subpane of the Test Bench pane of the Generate HDL dialog box, as shown below.

When you select the Multi-file test bench option, the Test bench data file name postfix option is enabled. The test bench file names are then derived from the name of the test bench, the Test bench name option, and the Test bench data file name postfix option as follows:

TestBenchName_TestBenchDataPostfix

For example, if the test bench name is my_fir_filt, and the target language is VHDL, the default test bench file names are:

  • my_fir_filt_tb.vhd: test bench code

  • my_fir_filt_tb_pkg.vhd: helper functions package

  • my_fir_filt_tb_data.vhd: data package

If the filter name is my_fir_filt and the target language is Verilog, the default test bench file names are:

  • my_fir_filt_tb.v: test bench code

  • my_fir_filt_tb_pkg.v: helper functions package

  • my_fir_filt_tb_data.v: test bench data

Command Line Alternative: Use the generatehdl properties MultifileTestBench, TestBenchDataPostFix, and TestBenchName to generate and name separate test bench helper functions, data, and test bench code files.

Configuring the Clock

Based on default settings, the coder configures the clock for a filter test bench such that it

  • Forces clock enable input signals to active high (1).

  • Asserts the clock enable signal 1 clock cycle after deassertion of the reset signal.

  • Forces clock input signals low (0) for a duration of 5 nanoseconds and high (1) for a duration of 5 nanoseconds.

To change these clock configuration settings:

  1. Click Configuration in the Test bench pane of the Generate HDL dialog box.

  2. Within the Test Bench pane, select the Configuration subpane.

  3. Make the following configuration changes as described in the following table:

    If You Want to...Then...
    Disable the forcing of clock enable input signalsClear Force clock enable.
    Disable the forcing of clock input signalsClear Force clock.
    Reset the number of nanoseconds during which clock input signals are to be driven low (0)Specify a positive integer or double (with a maximum of 6 significant digits after the decimal point) in the Clock low time field.
    Reset the number of nanoseconds during which clock input signals are to be driven high (1)Specify a positive integer or double (with a maximum of 6 significant digits after the decimal point) in the Clock high time field.
    Change the delay time elapsed between the deassertion of the reset signal and the assertion of clock enable signal.Specify a positive integer in the Clock enable delay field.

    The following figure highlights the applicable options.

Command Line Alternative: Use the generatehdl properties ForceClock, ClockHighTime, ClockLowTime, ForceClockEnable, and TestBenchClockEnableDelay to reconfigure the test bench clock.

Configuring Resets

Based on default settings, the coder configures the reset for a filter test bench such that it

  • Forces reset input signals to active high (1). (Test bench reset input levels are set by the Reset asserted level option).

  • Asserts reset input signals for a duration of 2 clock cycles.

  • Applies a hold time of 2 nanoseconds for reset input signals.

The hold time is the amount of time (after some number of initial clock cycles defined by the Reset length option) that reset input signals are to be held past the clock rising edge. The following figure shows the application of a hold time (thold) for reset input signals when the signals are forced to active high and active low. The default Reset length of 2 clock cycles is shown.

    Note:   The hold time applies to reset input signals only if the forcing of reset input signals is enabled.

The following table summarizes the reset configuration settings,

If You Want to...Then...
Disable the forcing of reset input signalsClear Force reset in the Test Bench pane of the Generate HDL dialog box.
Change the length of time (in clock cycles) during which reset is assertedSet Reset length (in clock cycles) to an integer greater than or equal to 0. This option is located in the Test Bench pane of the Generate HDL dialog box.
Change the reset value to active low (0)Select Active-low from the Reset asserted level menu in the Global Settings pane of the Generate HDL dialog box (see Setting the Asserted Level for the Reset Input Signal)
Set the hold timeSpecify a positive integer or double (with a maximum of 6 significant digits after the decimal point), representing nanoseconds, in the Hold time field. When the Hold time changes, the Setup time (ns) value (displayed below Hold time) is updated. The Setup time (ns) value computed as (clock period - HoldTime) in nanoseconds. These options are in the Test Bench pane of the Generate HDL dialog box.

The following figures highlight the applicable options.

    Note:   The hold time and setup time settings also apply to data input signals.

Command Line Alternative: Use the generatehdl properties ForceReset, ResetLength, and HoldTime to reconfigure test bench resets.

Setting a Hold Time for Data Input Signals

By default, the coder applies a hold time of 2 nanoseconds for filter data input signals. The hold time is the amount of time that data input signals are to be held past the clock rising edge. The following figure shows the application of a hold time (thold) for data input signals.

To change the hold time setting,

  1. Click the Test Bench tab in the Generate HDL dialog box.

  2. Within the Test Bench pane, select the Configuration subpane.

  3. Specify a positive integer or double (with a maximum of 6 significant digits after the decimal point), representing nanoseconds, in the Hold time field. In the following figure, the hold time is set to 2 nanoseconds.

    When the Hold time changes, the Setup time (ns) value (displayed below Hold time) updates. The coder computes the Setup time (ns) value as (clock period - HoldTime) in nanoseconds. Setup time (ns) is a display-only field.

    Note:   The hold time and setup time settings also apply to reset input signals, if the forcing of such signals is enabled.

Command Line Alternative: Use the generatehdl property HoldTime to adjust the hold time setting.

Setting an Error Margin for Optimized Filter Code

Customizations that provide optimizations can generate test bench code that produces numeric results that differ from results produced by the original filter object. These options include:

  • Optimize for HDL

  • FIR adder style set to Tree

  • Add pipeline registers for FIR, asymmetric FIR, and symmetric FIR filters

If you choose to use these options, consider setting an error margin for the generated test bench to account for differences in numeric results. The error margin is the number of least significant bits the test bench will ignore when comparing the results. To set an error margin:

  1. Select the Test Bench pane in the Generate HDL dialog box.

  2. Within the Test Bench pane, select the Configuration subpane.

  3. For fixed-point filters, the initial Error margin (bits) field has a default value of 4. If you wish to change the error margin, enter an integer in the Error margin (bits) field. In the following figure, the error margin is set to 4 bits.

Setting an Initial Value for Test Bench Inputs

By default, the initial value driven on test bench inputs is 'X' (unknown). Alternatively, you can specify that the initial value driven on test bench inputs is 0, as follows:

  1. Select the Test Bench pane in the Generate HDL dialog box.

  2. Within the Test Bench pane, select the Configuration subpane.

  3. To set an initial test bench input value of 0, select the Initialize test bench inputs option.

    To set an initial test bench input value of 'X', clear the Initialize test bench inputs option.

Command Line Alternative: Use the generatehdl property InitializeTestBenchInputs to set the initial test bench input value.

Setting Test Bench Stimuli

By default, the coder generates a filter test bench that includes stimuli that correspond to the given filter type. However, you can adjust the stimuli settings or specify user defined stimuli, if desired.

To modify the stimuli that the coder is to include in a test bench, select one or more response types listed in the Stimuli subpane of the Test bench settings pane of the Generate HDL dialog box. The following figure highlights this pane of the dialog box.

If you select User defined response, you must also specify an expression or function that returns a vector of values to be applied to the filter. The values specified in the vector are quantized and scaled based on the filter's quantization settings.

Command Line Alternative: Use the generatehdl properties TestBenchStimulus and TestBenchUserStimulus to adjust stimuli settings.

Setting a Postfix for Reference Signal Names

Reference signal data is represented as arrays in the generated test bench code. The string specified by Test bench reference postfix is appended to the generated signal names. The default string is _ref.

You can set the postfix string to a value other than _ref. To change the string:

  1. Select the Test Bench pane in the Generate HDL dialog box.

  2. Within the Test Bench pane, select the Configuration subpane.

  3. Enter a new string in the Test bench reference postfix field, as shown in the following figure.

Command Line Alternative: Use the function with the property TestBenchReferencePostFix to change the postfix string.

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