Documentation

Verification

HDL test bench generation, and cosimulation with third party EDA tools

Filter Design HDL Coder™ provides the option to generate a test bench for the generated HDL code for your filter. The test bench applies generated input stimuli to the HDL code generated for the filter. The test bench compares the output of the HDL filter implementation with saved result vectors from MATLAB® simulation. You can configure the clock and reset behavior, input stimulus, and file locations of the generated test bench.

Filter Design HDL Coder also provides cosimulation features to run your HDL simulation in Mentor Graphics® ModelSim®, or Cadence Incisive®, concurrently with Simulink®. Use this feature to verify that the HDL implementation of your feature works with other parts of your system design. This feature requires an HDL Verifier™ license.

Functions

generatetbstimulus Generate and return HDL test bench stimulus

Properties

Test Bench Properties Enable and customize generated test bench
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