This example guides you through the basic steps for setting up an HDL Verifier™ application using the Cosimulation Wizard.
This example use a MATLAB System object and ModelSim to verify a register transfer level (RTL) design of a Fast Fourier Transform (FFT) of size 8 written in Verilog. The FFT is commonly used in digital signal processing to produces frequency distribution of a signal.
To verify the correctness of this FFT, a MATLAB System object testbench is provided. This testbench generates a periodic sinusoidal input to the HDL design under test (DUT) and plots the Fourier Coefficients in the Complex Plane.
The Cosimulation Wizard takes the provided Verilog file of this FFT as its input. It also collects user input required for setting up cosimulation in each step. At the end of the example, the Cosimulation Wizard generates a MATLAB script that instantiates a configured HdlCosimulation System object, a MATLAB script that compiles HDL design, and a MATLAB script that launches the HDL simulator for cosimulation.
1. Set Up Example Files
To ensure that others can access copies of the example files, set up a folder for your own example work by following these instructions:
a. Create a folder outside the scope of your MATLAB installation folder into which you can copy the example files. The folder must be writable. This example assumes that you create a folder named 'MyTests'.
b. Copy all the files located in the following directory to the folder you created:
c. You now have all the example files you need in your working directory:
2. Launch Cosimulation Wizard
a. Start MATLAB.
b. Set the directory you created in Set Up Example Files as your current directory in MATLAB.
c. At the MATLAB command prompt, enter the following:
The command launches the Cosimulation Wizard.
3. Specify Cosimulation Type
In the Cosimulation Type page, perform the following steps:
a. Change HDL cosimulation with option set to MATLAB System Object.
b. If you are using ModelSim, change HDL Simulator option as ModelSim.
c. Leave the default option Use HDL simulator executables on the system path option if the HDL simulator executables appear on your system path. If these executable do not appear on the path, specify the HDL simulator path.
d. Click Next to proceed to the HDL Files page.
4. Select HDL Files
In the HDL Files page, perform the following steps:
a. Add HDL files to file list:
Click Add and select the Verilog files fft_hdl.v and fft_hdl_tc.v in your example folder.
Review the files in the file list to make sure the file type is correctly identified.
b. Click Next to proceed to the HDL Compilation page.
5. Specify HDL Compilation Commands
The Cosimulation Wizard lists the default commands in the Compilation Commands window. You do not need to change these commands for this example.
Click Next. The MATLAB console displays the compilation log. If an error occurs during compilation, that error appears in the Status area. Correct the error before proceeding to the next step.
6. Select HDL Modules for Cosimulation
In the HDL Modules page, perform the following steps:
a. Specify the name of HDL module/entity for cosimulation. From the drop-down list, select fft_hdl. This module is the Verilog module you use for cosimulation. If you do not see "fft_hdl" in the drop-down list, you can enter the file name manually.
b. In the Simulation options field, remove the -novopt option so that ModelSim can optimize the HDL design.
c. Click Next. The Cosimulation Wizard launches the HDL simulator in the background console using the specified HDL module and simulation options. If the wizard launches the HDL simulator successfully, the wizard populates the input and output ports on the Verilog model fft_hdl and displays them in the next step.
7. Specify Input/Output Port Types
In this step, the Cosimulation Wizard displays two tables containing the input and output ports of fft_hdl, respectively.
The Cosimulation Wizard attempts to correctly identify the port type for each port. If the wizard incorrectly identifies a port, you can change the port type using these tables.
For input ports, you can select from Clock, Reset, Input, or Unused. HDL Verifier connects only the input ports marked "Input" to MATLAB during cosimulation.
HDL Verifier connects output ports marked Output with MATLAB during cosimulation. The link software and MATLAB ignore those output ports marked "Unused during cosimulation.
You can change the parameters for signals identified as "Clock" and "Reset" at a later step.
Accept the default port types and click Next to proceed to the Output Port Details page.
8. Specify Output Port Details
For this example, the HDL FFT outputs are signed, 13 bits long with 9 bits of fraction length. In the Output Port Details page, perform the following steps:
a. Note that the Sample Time can not be changed and is always fixed to 1 with the HdlCosimulation System object .
b. Change the Data Type to Signed for both outputs
c. Change the Fraction Length to 9 for both outputs
c. Click Next to proceed to the Clock/Reset Details page.
9. Set Clock and Reset Details
Set the clock Period (ns) to 20. From the Verilog code, you know that the reset is synchronous and the active value is 1. You can reset the entire HDL design at time 1 ns, triggered by the rising edge of the clock. Use a duration of 15 ns for the reset signal. In the Clock/Reset Details page, perform the following steps:
a. Set clock period to 20.
b. Leave or set active edge to Rising.
c. Leave or set reset initial value to 1.
d. Set reset signal duration to 15.
Click Next to proceed to the Start Time Alignment page.
10. Confirm Start Time Alignment
The Start Time Alignment page displays a plot for the waveforms of clock and reset signals. The Cosimulation Wizard shows the HDL time to start cosimulation with a red line. The start time is also the time at which the System object gets the first input sample from the HDL simulator. The active edge of clock is a rising edge. Thus, at time 20 ns in the HDL simulator, the registered output of the FFT is stable. No race condition exists, and the default HDL time to start cosimulation (20 ns) is correct.
Click Next to proceed to System Object Generation.
11. Generate System Object
a. Before Cosimulation Wizard generates the scripts, you have the option to modify the HDL Simulator sampling period. The sampling period determine the elapsed time in the HDL Simulator separating each call to step in MATLAB. Most of the time the sampling period is equal to the clock period. You can also specify if your inputs/outputs are frame based (instead of sample based).
b. Click Finish to complete the Cosimulation Wizard session.
12. Create Test Bench to Verify HDL Design
For this example, you do not actually create the test bench. Instead, you can find the finished script fft_tb.m in the directory you created in Set Up Example Files.
a. After you click Finish in the Cosimulation Wizard, the application generates three HDL files in the current directory:
compile_hdl_design_fft_hdl.m: To recompile the HDL design
launch_hdl_simulator_fft_hdl.m: To relaunch the MATLAB System object server and start the HDL simulator.
hdlcosim_fft_hdl.m: To create the HdlCosimulation System object
b. Open the files fft_tb.m and hdlcosim_fft_hdl.m, located in the directory you created in Set Up Example Files and observe the HdlCosimulation System object calls. hdlcosim_fft_hdl.m contains the HdlCosimulation instanciation and fft_tb.m contains a MATLAB System object test bench. You will use this test bench to verify the HDL design for which you just generated a corresponding HdlCosimulation System object .
13. Run Cosimulation and Verify HDL Design
a. Launch the HDL simulator by executing the script launch_hdl_simulator_fft_hdl.m.
b. When the HDL simulator is ready, return to MATLAB and start the simulation by executing the script fft_tb.m.
c. Verify the result from the plot in the test bench. The plot display the Fourier Coefficients in the Complex Plane.
This concludes the Cosimulation Wizard for use with MATLAB System object example.