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Frame-based Scrambler Using Communications System Toolbox™

This example illustrates the validation of an HDL implementation of a 6-order scrambler. A scrambler is used in communication systems to randomize transitions in the transmitted signal by shuffling the bits. One purpose of scrambling is to reduce the length of strings of 0s or 1s in a transmitted signal, since a long string of 0s or 1s may cause transmission synchronization problems. Scrambling may also be used as a cheap encryption technique. This example consists of two models. The first model (scrambler_frame) validates the HDL implementation and the second model (scrambler_fsk) uses the HDL scrambler as part of a communication channel.

You need the following products to run this example:


  • Simulink

  • Communications System Toolbox

  • HDL Verifier

  • Cadence Incisive software

HDL Implementation and Validation

The scrambler_frame model illustrates the validation of an HDL implementation of a 6-order scrambler. The handwritten HDL code is intended to replicate the behavior of the Scrambler block in Communications System Toolbox™. The HDL Verifier™ software is used here as a validation tool to test the functional equivalence of the HDL scrambler to the Communications System Toolbox scrambler.

The model generates a binary sequence and simultaneously drives it to the HDL implementation and the original Simulink® block. Two copies of the Descrambler block from Communications System Toolbox are used to reconstitute the original data stream from the outputs of the two scramblers. The outputs are compared to the input data sequence to detect any discrepancies that may be introduced by differences between the scramblers using the Error Calculation block. Because the HDL Cosimulation block always delays the data by one frame, we delay the data in all other branches so that the comparison will be valid.

Channel Encoding with an HDL Scrambler Block

The scrambler_fsk model shows the use of a Scrambler as part of a communication channel. The block of interest is a 6-order scrambler implemented in HDL and cosimulated with Simulink by the HDL Verifier software. It has previously been verified to be functionally equivalent to the Scrambler block in the Communications System Toolbox. The Descrambler block is from the Communications System Toolbox and is also of order-6. The channel uses 11 bits per frame and BCH 11-->31 bits encoding (and the opposite BCH 31-->11 bits decoding). This encoding method is theoretically able to correct burst errors with up to 5 flipped bits. The data is passed through a channel with burst errors of 6 consecutive bits (i.e., 6 out of 11 bits in each frame will be flipped).

The data is then transmitted using 2-ary FSK modulator and demodulator blocks and a Gaussian channel with a very high signal-to-noise ratio, so we assume that almost all errors are burst errors and not Gaussian white noise errors. The locations of the flipped bits are randomly chosen in each frame. Since the current encoding configuration cannot fix all errors when 6 bits are flipped, there will be some errors after decoding the data and the BER (Bit Error Rate) will not be zero. The model contains 2 channels: one includes Scrambler / Descrambler blocks and the other one does not. In the case of our model, it is clear that the BER is improved (becomes lower) when we use the Scrambler / Descrambler blocks as part of our communication channel.

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