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Functionally-Timed SystemC/TLM Simulation

This example highlights the use of the 'Timed' timing mode without the use of temporally decoupled initiators when you generate a SystemC™/TLM component from a Simulink model using the tlmgenerator target for either Simulink Coder or Embedded Coder™.

In Simulink® models, the movement of data between sources and sinks is controlled by signal sample rates and a centralized timing solver. In SystemC/TLM models, interactions between data sinks and sources are controlled by the SystemC simulation kernel and time advances through SC_THREADs cooperatively yielding control to another thread through wait calls.

For timed SystemC/TLM simulations the model adheres to the annotated delays for communication interfaces and processing. For functionally-timed simulations, the model does not allow threads to "run ahead" in time as in loosely-timed simulations and so there is no idea of a "local time" that is different than some other thread's sense of time. Instead, initiators immediately synchronize to the returned delays from TLM transactions and generally perform non-zero timed waits in order to execute polling loops and sychronization-on-demand. The goal of the model, in addition to proper synchronization of data movement as with the untimed system, is to gain some sense of the performance of the deployed system and potentially to examine certain architectural choices. Simulation time will advance in a functionally-timed model to reflect communication, processing, and polling delays in the system.

For this example we use a Simulink model of a FIR filter as the basis of the SystemC/TLM generation.

Products required to run this demo:

  • MATLAB

  • Simulink

  • Simulink Coder

  • HDL Verifier

  • SystemC 2.3 (includes the TLM library)

Note: The example includes a code generation build procedure. Simulink does not permit you to build programs in the MATLAB installation area. If necessary, change to a working directory that is not in the MATLAB installation area prior to starting any build.

1. Open the Preconfigured Model

Open the TLM functionally-timed testbench modelTLM functionally-timed testbench model or in the MATLAB command window execute:

  >> openTlmgDemoModel('fttb')

The following model opens in Simulink.

2. Review the TLM Generator Target Configuration Options

In the model window, from the Simulation menu select Model Configuration Parameters... In the Configuration Parameters dialog box, select the TLM Generator view and then tab TLM Testbench view and review the testbench settings as shown in the following image. Select the verbose testbench message checkbox to see the full log of initiator/target interaction in the SystemC/TLM simulation. Since this will be thousands of lines, if desired, deselect the option to get a terse log of the SystemC/TLM simulation.

3. Build the Model

In the model window, right-click on the DualFilter block and select C/C++ Code > Build This Subsystem in the context menu to start the TLM component and testbench generationTLM component and testbench generation. Or you can execute the following command in the MATLAB command window:

  >> buildTlmgDemoModel('fttb')

The generation is completed when the following message appears in the MATLAB command window:

### Starting Simulink Coder build procedure for model: DualFilter
### Successful completion of Simulink Coder build procedure for model: DualFilter

4. Open the Generated Files

Open the generated testbench source code in the MATLAB web browser by clicking on 'DualFilter_fttb_tlm_tb.cpp' in the generated report or in the MATLAB Editor:

5. Review the Generated Code

The specification of 'With timing' results in the testbench instructing the TLM component to run in timed mode by means of a special configuration interface, mw_backdoorcfg_IF. As the code indicates, the choice of timing mode is dynamic and can be changed during the course of simulation. Since this choice is purely a simulation construct, it is not programmed by means of a "front-door" TLM transaction.

Additionally, as the code indicates, the testbench must setup a local helper object with the correct timing mode in order to ensure that its initiator threads use the proper synchronization in the TLM transaction calls.

The implementation of the functionally-timed synchronization class, mw_syncfunctimed_tb, in the mw_support_tb.cpp file shows the details of the various synchronization calls used by the initiator threads and the TLM transactions. Unlike untimed simulations, the calls utilize waits of non-zero times, but, as with untimed simulations, no "local time" delays are allowed to accumulate.

6. Verify the Generated Code

In the Configuration Parameters dialog box, go in TLM Testbench configuration parameter dialog and push the Verify TLM Component button to run the generated testbench in the functionally-timed timing moderun the generated testbench in the functionally-timed timing mode or in the MATLAB command window execute:

  >> verifyTlmgDemoModel('fttb')

This action will:

  • build the generated code

  • run Simulink to capture input stimulus and expected results

  • convert the Simulink data to TLM vectors

  • run the stand-alone SystemC/TLM testbench executable

  • convert the TLM results back to Simulink data

  • perform a data comparison

  • generate a Figure window for any signals that had data mis-compares

7. Review the Execution Log

The option to generate verbose messages was selected in order to see how the testbench initiator threads interact and synchronize with the target. In the functionally-timed simulation, notice how the initiators immediately synchronize to the annotated delay returned from the TLM transactions. Also, all polling and timed waits are immediate, non-zero sim-time synchronization points.

### Starting component verification
### Checking available compiler.
### Building testbench and TLM component.
### Running Simulink simulation to capture inputs and expected outputs.
### Executing TLM testbench to generate actual outputs.

             SystemC 2.3.0-ASI --- Aug 15 2012 14:40:01
        Copyright (c) 1996-2012 by all Contributors,
        ALL RIGHTS RESERVED

[       0 s] (readerThread) 		## found input field tlmg_in1 at tlmg_tlminvec fieldnum 0
[       0 s] (readerThread) 		## found input field tlmg_in2 at tlmg_tlminvec fieldnum 1
[       0 s] (readerThread) 		## found output field tlmg_out1 at tlmg_tlminvec fieldnum 2
[       0 s] (readerThread) 		## found output field tlmg_out2 at tlmg_tlminvec fieldnum 3
[       0 s] (readerThread) 		## setup 2 input data fields, 2 output data fields
## STARTING SIMULATION
[       0 s] (writerThread) ## Start of vectors from MAT file.  Will display '.' for every 100 vectors played.
[       0 s] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 5 ns).
[     10 ns] (writerThread) ##	 TLM write transaction to target component at address 0x000020
[     10 ns] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[     10 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[     10 ns] (writerThread) ## vec     0:
##	 initialized input dataset
[     10 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[     10 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00112200)
[     10 ns] (readerThread) 		##	 syncing to local time offset (delay = 5 ns).
[     20 ns] (readerThread) 		##	 TLM write transaction to target component at address 0x000020
[     20 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00112200)
[     20 ns] (readerThread) 		##	 syncing to local time offset (delay = 0 s).
[     20 ns] (readerThread) 		##	 syncing to interrupt signal for data ready in output buffer...
[     30 ns] (writerThread) ##	 TLM write transaction to target component at address 00000000
[     30 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[     30 ns] (writerThread) ## vec     1:
##	 initialized input dataset
[     50 ns] (writerThread) ##	 TLM write transaction to target component at address 00000000
[     50 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[     50 ns] (writerThread) ## vec     2:
##	 initialized input dataset
[     70 ns] (writerThread) ##	 TLM write transaction to target component at address 00000000
[     70 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[     70 ns] (writerThread) ##	 waiting for explicit amount of time (time = 0 s + 300 ns).
[    130 ns] (readerThread) 		##	...saw interrupt
[    130 ns] (readerThread) 		##	 syncing to local time offset (delay = 0 s).
[    130 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[    130 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00002204)
[    130 ns] (readerThread) 		##	 syncing to local time offset (delay = 5 ns).
[    135 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000010
[    135 ns] (readerThread) 		##	 syncing to local time offset (delay = 20 ns).
[    155 ns] (readerThread) 		##	 wrote actual output dataset to MAT file buffer.
[    155 ns] (readerThread) 		##	 initialized expected output dataset
[    155 ns] (readerThread) 		##	 actual output dataset matched expected output dataset
[    155 ns] (readerThread) 		##	 syncing to local time offset (delay = 0 s).
[    155 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[    155 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00102200)
[    155 ns] (readerThread) 		##	 syncing to local time offset (delay = 5 ns).
[    160 ns] (readerThread) 		##	 syncing to interrupt signal for data ready in output buffer...
[    230 ns] (readerThread) 		##	...saw interrupt
[    230 ns] (readerThread) 		##	 syncing to local time offset (delay = 0 s).
[    230 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[    230 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00012204)
[    230 ns] (readerThread) 		##	 syncing to local time offset (delay = 5 ns).
[    235 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000010
[    235 ns] (readerThread) 		##	 syncing to local time offset (delay = 20 ns).
[    255 ns] (readerThread) 		##	 wrote actual output dataset to MAT file buffer.
[    255 ns] (readerThread) 		##	 initialized expected output dataset
[    255 ns] (readerThread) 		##	 actual output dataset matched expected output dataset
[    255 ns] (readerThread) 		##	 syncing to local time offset (delay = 0 s).
[    255 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[    255 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00112200)
[    255 ns] (readerThread) 		##	 syncing to local time offset (delay = 5 ns).
[    260 ns] (readerThread) 		##	 syncing to interrupt signal for data ready in output buffer...
[    330 ns] (readerThread) 		##	...saw interrupt
[    330 ns] (readerThread) 		##	 syncing to local time offset (delay = 0 s).
[    330 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[    330 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00012204)
[    330 ns] (readerThread) 		##	 syncing to local time offset (delay = 5 ns).
[    335 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000010
[    335 ns] (readerThread) 		##	 syncing to local time offset (delay = 20 ns).
[    355 ns] (readerThread) 		##	 wrote actual output dataset to MAT file buffer.
[    355 ns] (readerThread) 		##	 initialized expected output dataset
[    355 ns] (readerThread) 		##	 actual output dataset matched expected output dataset
[    355 ns] (readerThread) 		##	 syncing to local time offset (delay = 0 s).
[    355 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[    355 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00112200)
[    355 ns] (readerThread) 		##	 syncing to local time offset (delay = 5 ns).
[    360 ns] (readerThread) 		##	 syncing to interrupt signal for data ready in output buffer...
[    370 ns] (writerThread) ##	 polling for input and output buffers empty...
[    370 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[    370 ns] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[    370 ns] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[    370 ns] (writerThread) ##	 syncing to local time offset (delay = 5 ns).
[    375 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[    375 ns] (writerThread) ##	...saw polling return expected value. (bitValue=0x00110000, bitMask=0x00110000, masked csr=0x00110000)
[    375 ns] (writerThread) ## vec     3:
##	 initialized input dataset
[    395 ns] (writerThread) ##	 TLM write transaction to target component at address 00000000
[    395 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[    395 ns] (writerThread) ## vec     4:
##	 initialized input dataset
[    415 ns] (writerThread) ##	 TLM write transaction to target component at address 00000000
[    415 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[    415 ns] (writerThread) ## vec     5:
##	 initialized input dataset


<<<<<<<<<<<  SNIP >>>>>>>>>>>>>>

[  60920 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00012204)
[  60920 ns] (readerThread) 		##	 syncing to local time offset (delay = 5 ns).
[  60925 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000010
[  60925 ns] (readerThread) 		##	 syncing to local time offset (delay = 20 ns).
[  60945 ns] (readerThread) 		##	 wrote actual output dataset to MAT file buffer.
[  60945 ns] (readerThread) 		## end of output vectors in MAT file vectors/tlmg_tlminvec.mat for output number 0
[  60945 ns] (readerThread) 		## end of output vectors in MAT file vectors/tlmg_tlminvec.mat for output number 1
[  60945 ns] (readerThread) 		##	 initialized expected output dataset
[  60945 ns] (readerThread) 		##	 actual output dataset matched expected output dataset
[  60945 ns] (readerThread) 		##	 syncing to local time offset (delay = 0 s).
[  60945 ns] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[  60945 ns] (readerThread) 		##	 (Command/Status reg data value = 0x00112200)
[  60945 ns] (readerThread) 		##	 syncing to local time offset (delay = 5 ns).
[  60950 ns] (readerThread) 		## end of output data...Terminating readerThread
[  60950 ns] (readerThread) 		
#############################################
## END OF VECTORS. PLAYED   501 VECTORS.   ##
## DATA MISCOMPARES     :     0            ##
## TRANSPORT ERRORS     :    NO            ##
## MAT FILE WRITE ERRORS:    NO            ##
#############################################
[  60950 ns] (readerThread) 		##	 Wrote results MAT file.
[  60960 ns] (writerThread) ##	 polling for input and output buffers empty...
[  60960 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[  60960 ns] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[  60960 ns] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[  60960 ns] (writerThread) ##	 syncing to local time offset (delay = 5 ns).
[  60965 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[  60965 ns] (writerThread) ##	...saw polling return expected value. (bitValue=0x00110000, bitMask=0x00110000, masked csr=0x00110000)
[  60965 ns] (writerThread) ## end of input vectors in MAT file vectors/tlmg_tlminvec.mat for input number 0
[  60965 ns] (writerThread) ## end of input vectors in MAT file vectors/tlmg_tlminvec.mat for input number 1
[  60965 ns] (writerThread) ##	 waiting for explicit amount of time (time = 0 s + 300 ns).
[  61265 ns] (writerThread) ##	 polling for input and output buffers empty...
[  61265 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[  61265 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[  61265 ns] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[  61265 ns] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[  61265 ns] (writerThread) ##	 syncing to local time offset (delay = 5 ns).
[  61270 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[  61270 ns] (writerThread) ##	...saw polling return expected value. (bitValue=0x00110000, bitMask=0x00110000, masked csr=0x00110000)
[  61270 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[  61270 ns] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[  61270 ns] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[  61270 ns] (writerThread) ##	 syncing to local time offset (delay = 5 ns).
[  61275 ns] (writerThread) ##	 syncing to local time offset (delay = 0 s).
[  61275 ns] (writerThread) ## end of data...Terminating initiator thread.
## SIMULATION HAS ENDED
### Comparing expected vs. actual results.
Data successfully compared for signal tlmg_out1.
Data successfully compared for signal tlmg_out2.
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