Documentation

Loosely-Timed SystemC/TLM Simulation

This example highlights the use of the 'Timed' timing mode when you generate a SystemC™/TLM component from a Simulink model using the tlmgenerator target for either Simulink Coder or Embedded Coder™.

In Simulink® models, the movement of data between sources and sinks is controlled by signal sample rates and a centralized timing solver. In SystemC/TLM models, interactions between data sinks and sources are controlled by the SystemC simulation kernel and time advances through SC_THREADs cooperatively yielding control to another thread through wait calls.

For timed SystemC/TLM simulations the model adheres to the annotated delays for communication interfaces and processing. For loosely-timed simulations, the model does not allow threads to "run ahead" in time and so there is no idea of a "local time" that is different than some other thread's sense of time. Instead, initiators immediately synchronize to the returned delays from TLM transactions and generally perform non-zero timed waits in order to execute polling loops and synchronization-on-demand. Simulation time will advance in a loosely-timed model to reflect communication, processing, and polling delays in the system. The goal of the model, in addition to proper synchronization of data movement as with the untimed system, is to have a functionally correct simulation with a fast wall-clock execution times. This speed allows for near real-time software development on the SystemC/TLM architectural model.

For this example we use a Simulink model of a FIR filter as the basis of the SystemC/TLM generation.

Products required to run this demo:

  • MATLAB

  • Simulink

  • Simulink Coder

  • HDL Verifier

  • SystemC 2.3.1 (includes the TLM library)

  • For code verification, make and a compatible GNU-compiler, gcc, in your path on Linux®, or Visual Studio® compiler in your path on Windows®

Note: The example includes a code generation build procedure. Simulink does not permit you to build programs in the MATLAB installation area. If necessary, change to a working directory that is not in the MATLAB installation area prior to starting any build.

1. Open the Preconfigured Model

Open the TLM loosely-timed testbench model or in the MATLAB command window execute:

  >> openTlmgDemoModel('lttb')

The following model opens in Simulink.

2. Review the TLM Generator Target Configuration Options

In the model window, from the Simulation menu select Model Configuration Parameters... In the Configuration Parameters dialog box, select the TLM Generator view and then tab TLM Testbench view and review the testbench settings as shown in the following image. Select the verbose testbench message checkbox to see the full log of initiator/target interaction in the SystemC/TLM simulation. Since this will be thousands of lines, if desired, deselect the option to get a terse log of the SystemC/TLM simulation.

3. Build the Model

In the model window, right-click on the DualFilter block and select C/C++ Code > Generate Code for this Subsystem in the context menu to start the TLM component and testbench generation. Or you can execute the following command in the MATLAB command window:

  >> buildTlmgDemoModel('lttb')

The generation is completed when the following message appears in the MATLAB command window:

### Starting Simulink Coder build procedure for model: DualFilter
### Successful completion of Simulink Coder build procedure for model: DualFilter

4. Open the Generated Files

Open the generated testbench source code in the MATLAB web browser by clicking on 'DualFilter_lttb_tlm_tb.cpp' in the generated report or in the MATLAB Editor:

5. Review the Generated Code

The specification of 'With timing' results in the testbench instructing the TLM component to run in timed mode by means of a special configuration interface, mw_backdoorcfg_IF. As the code indicates, the choice of timing mode is dynamic and can be changed during the course of simulation. Since this choice is purely a simulation construct, it is not programmed by means of a "front-door" TLM transaction.

Additionally, as the code indicates, the testbench must setup a local helper object with the correct timing mode in order to ensure that its initiator threads use the proper synchronization in the TLM transaction calls.

The implementation of the loosely-timed synchronization class, mw_syncfunctimed_tb, in the mw_support_tb.cpp file shows the details of the various synchronization calls used by the initiator threads and the TLM transactions. Unlike untimed simulations, the calls utilize waits of non-zero times, but, as with untimed simulations, no "local time" delays are allowed to accumulate.

6. Verify the Generated Code

In the Configuration Parameters dialog box, go in TLM Testbench configuration parameter dialog and push the Verify TLM Component button to run the generated testbench in the loosely-timed timing mode or in the MATLAB command window execute:

  >> verifyTlmgDemoModel('lttb')

This action will:

  • build the generated code

  • run Simulink to capture input stimulus and expected results

  • convert the Simulink data to TLM vectors

  • run the stand-alone SystemC/TLM testbench executable

  • convert the TLM results back to Simulink data

  • perform a data comparison

  • generate a Figure window for any signals that had data mis-compares

7. Review the Execution Log

The option to generate verbose messages was selected in order to see how the testbench initiator threads interact and synchronize with the target. In the loosely-timed simulation, notice how the initiators immediately synchronize to the annotated delay returned from the TLM transactions. Also, all polling and timed waits are immediate, non-zero sim-time synchronization points.

### Starting component verification
### Checking available compiler.
### Building testbench and TLM component.
### Running Simulink simulation to capture inputs and expected outputs.
### Executing TLM testbench to generate actual outputs.
 
        SystemC 2.3.1-Accellera --- Dec  4 2015 16:22:19 
        Copyright (c) 1996-2014 by all Contributors, 
        ALL RIGHTS RESERVED 
[       0 s] (singleInitiatorThread) ## found input field tlmg_in1 at tlmg_tlminvec fieldnum 0 
[       0 s] (singleInitiatorThread) ## found input field tlmg_in2 at tlmg_tlminvec fieldnum 1 
[       0 s] (singleInitiatorThread) ## found output field tlmg_out1 at tlmg_tlminvec fieldnum 2 
[       0 s] (singleInitiatorThread) ## found output field tlmg_out2 at tlmg_tlminvec fieldnum 3 
[       0 s] (singleInitiatorThread) ## setup 2 input data fields, 2 output data fields 
## STARTING SIMULATION 
[       0 s] (singleInitiatorThread) ## Start of vectors from MAT file.  Will display '.' for every 100 vectors played. 
[       0 s] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000020 
[       0 s] (singleInitiatorThread) ##	 (Command/Status reg data value = 0x00112200) 
[       0 s] (singleInitiatorThread) ##	 syncing to local time offset (delay = 5 ns). 
[     10 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 0x000020 
[     10 ns] (singleInitiatorThread) ##	 (Command/Status reg data value = 0x00112200) 
[     10 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[     10 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000020 
[     10 ns] (singleInitiatorThread) ##	 (Command/Status reg data value = 0x00112200) 
[     10 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 5 ns). 
[     20 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 0x000020 
[     20 ns] (singleInitiatorThread) ##	 (Command/Status reg data value = 0x00112200) 
[     20 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[     20 ns] (singleInitiatorThread) ## vec     0: 
##	 initialized input dataset 
[     40 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 00000000 
[     40 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[     40 ns] (singleInitiatorThread) ##	 syncing to interrupt signal for data ready in output buffer... 
[    140 ns] (singleInitiatorThread) ##	...saw interrupt 
[    140 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[    140 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[    160 ns] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[    160 ns] (singleInitiatorThread) ##	 initialized expected output dataset 
[    160 ns] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 
[    160 ns] (singleInitiatorThread) ## vec     1: 
##	 initialized input dataset 
[    180 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 00000000 
[    180 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[    180 ns] (singleInitiatorThread) ##	 syncing to interrupt signal for data ready in output buffer... 
[    280 ns] (singleInitiatorThread) ##	...saw interrupt 
[    280 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[    280 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[    300 ns] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[    300 ns] (singleInitiatorThread) ##	 initialized expected output dataset 
[    300 ns] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 
[    300 ns] (singleInitiatorThread) ## vec     2: 
##	 initialized input dataset 
[    320 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 00000000 
[    320 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[    320 ns] (singleInitiatorThread) ##	 syncing to interrupt signal for data ready in output buffer... 
[    420 ns] (singleInitiatorThread) ##	...saw interrupt 
[    420 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[    420 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[    440 ns] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[    440 ns] (singleInitiatorThread) ##	 initialized expected output dataset 
[    440 ns] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 
[    440 ns] (singleInitiatorThread) ## vec     3: 
##	 initialized input dataset 
[    460 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 00000000 
[    460 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[    460 ns] (singleInitiatorThread) ##	 syncing to interrupt signal for data ready in output buffer... 
[    560 ns] (singleInitiatorThread) ##	...saw interrupt 
[    560 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[    560 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[    580 ns] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[    580 ns] (singleInitiatorThread) ##	 initialized expected output dataset 
[    580 ns] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 
[    580 ns] (singleInitiatorThread) ## vec     4: 
##	 initialized input dataset 
[    600 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 00000000 
[    600 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[    600 ns] (singleInitiatorThread) ##	 syncing to interrupt signal for data ready in output buffer... 
[    700 ns] (singleInitiatorThread) ##	...saw interrupt 
[    700 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[    700 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[    720 ns] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[    720 ns] (singleInitiatorThread) ##	 initialized expected output dataset 
[    720 ns] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 
[    720 ns] (singleInitiatorThread) ## vec     5: 
##	 initialized input dataset 
[    740 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 00000000 
[    740 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[    740 ns] (singleInitiatorThread) ##	 syncing to interrupt signal for data ready in output buffer... 
[    840 ns] (singleInitiatorThread) ##	...saw interrupt 
[    840 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[    840 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[    860 ns] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[    860 ns] (singleInitiatorThread) ##	 initialized expected output dataset 
[    860 ns] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 
[    860 ns] (singleInitiatorThread) ## vec     6: 
##	 initialized input dataset 
[    880 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 00000000 
[    880 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[    880 ns] (singleInitiatorThread) ##	 syncing to interrupt signal for data ready in output buffer... 
[    980 ns] (singleInitiatorThread) ##	...saw interrupt 
[    980 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[    980 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[      1 us] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[      1 us] (singleInitiatorThread) ##	 initialized expected output dataset 
[      1 us] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 


<<<<<<<<<<<  SNIP >>>>>>>>>>>>>>

[  69860 ns] (singleInitiatorThread) ##	...saw interrupt 
[  69860 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[  69860 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[  69880 ns] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[  69880 ns] (singleInitiatorThread) ##	 initialized expected output dataset 
[  69880 ns] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 
[  69880 ns] (singleInitiatorThread) ## vec   499: 
##	 initialized input dataset 
[  69900 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 00000000 
[  69900 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[  69900 ns] (singleInitiatorThread) ##	 syncing to interrupt signal for data ready in output buffer... 
[     70 us] (singleInitiatorThread) ##	...saw interrupt 
[     70 us] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[     70 us] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[  70020 ns] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[  70020 ns] (singleInitiatorThread) ##	 initialized expected output dataset 
[  70020 ns] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 
[  70020 ns] (singleInitiatorThread) ## vec   500: 
##	 initialized input dataset 
[  70020 ns] (singleInitiatorThread) . 
[  70040 ns] (singleInitiatorThread) ##	 TLM write transaction to target component at address 00000000 
[  70040 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[  70040 ns] (singleInitiatorThread) ##	 syncing to interrupt signal for data ready in output buffer... 
[  70140 ns] (singleInitiatorThread) ##	...saw interrupt 
[  70140 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000010 
[  70140 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 20 ns). 
[  70160 ns] (singleInitiatorThread) ##	 wrote actual output dataset to MAT file buffer. 
[  70160 ns] (singleInitiatorThread) ## end of output vectors in MAT file vectors/tlmg_tlminvec.mat for output number 0 
[  70160 ns] (singleInitiatorThread) ## end of output vectors in MAT file vectors/tlmg_tlminvec.mat for output number 1 
[  70160 ns] (singleInitiatorThread) ##	 initialized expected output dataset 
[  70160 ns] (singleInitiatorThread) ##	 actual output dataset matched expected output dataset 
[  70160 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[  70160 ns] (singleInitiatorThread) ##	 TLM read  transaction to target component at address 0x000020 
[  70160 ns] (singleInitiatorThread) ##	 (Command/Status reg data value = 0x00112200) 
[  70160 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 5 ns). 
[  70165 ns] (singleInitiatorThread) ##	 syncing to local time offset (delay = 0 s). 
[  70165 ns] (singleInitiatorThread) ## end of data...Terminating initiator thread. 
[  70165 ns] (singleInitiatorThread)  
############################################# 
## END OF VECTORS. PLAYED   501 VECTORS.   ## 
## DATA MISCOMPARES     :     0            ## 
## DATA MISCOMPARES     :     0            ## 
## TRANSPORT ERRORS     :    NO            ## 
## MAT FILE WRITE ERRORS:    NO            ## 
############################################# 
[  70165 ns] (singleInitiatorThread) ##	 Wrote results MAT file. 
## SIMULATION HAS ENDED 
### Comparing expected vs. actual results.
Data successfully compared for signal tlmg_out1.
Data successfully compared for signal tlmg_out2.
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