Documentation

This is machine translation

Translated by Microsoft
Mouseover text to see original. Click the button below to return to the English verison of the page.

Note: This page has been translated by MathWorks. Please click here
To view all translated materals including this page, select Japan from the country navigator on the bottom of this page.

Manchester Receiver Using Mixed Design (Verilog and VHDL)

This example shows verification of a Manchester enocder using mixed HDL languages, VHDL and Verilog. Manchester encoding is a simple modulation scheme which converts baseband digital data into an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

This model simulates a pure-digital receiver of Manchester encoded data. The receiver is implemented in VHDL/Verilog. The receiver uses a simple DLL clock recovery mechanism, which requires multiple cycles to lock with the incoming data stream. The performance of the receiver is explored by applying phase and frequency errors to a randomly generated steam of bits that is encoded using a simple MATLAB® function: manchesterencoder().

The actual VHDL/Verilog code will run in ModelSim® using the cosimulation block called "Mixed HDL Manchester Receiver"

Was this topic helpful?