This example illustrates verification of a receiver of Manchester encoded data. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.
This model simulates a digital receiver of Manchester encoded data. The receiver is implemented in HDL. The receiver uses a simple DLL (delay lock loop) clock recovery mechanism, which requires multiple cycles to lock with the incoming data stream. The performance of the receiver is explored by applying phase and frequency errors to a randomly generated stream of bits that is encoded using a simple MATLAB® function: manchesterencoder().
We illustrate different ways to partition the design in HDL and connect to those designs via the HDL Verifier™ cosimulation block.
Products required to run this example:
DSP System Toolbox
Cadence Incisive simulator
The HDL code runs in the Incisive® simulator as a single HDL Verifier HDL cosimulation block labeled "HDL Manchester Receiver". Here, Simulink® signals are mapped to the top-level HDL block.
Open the Manchester model and follow the steps outlined in the 'Running a Cosimulation' annotation.
In this part of the example, the same Manchester system is used, but it utilizes multiple HDL modules to implement the receiver functionality. The top-level wiring for the Receiver Subsystem is done in Simulink instead of the HDL.
The HDL code runs in the Incisive simulator and its execution is reflected in Simulink as the behaviors of three HDL Cosimulation blocks under the Manchester Receiver Subsystem. They are labeled State Counter, IQ Converter and Decoder.
Open the multiple-block model and follow the steps outlined in the 'Running a Cosimulation' annotation.
In this part of the example, the same Manchester system is used, but it uses design files that are a mixture of Verilog and VHDL. In this example VHDL implementations are used for the lower level blocks and the top block implementation is in Verilog. Connections are made to some signals in Verilog and others in VHDL via the ports pane of the HDL Verifier block. In spite of the differences in HDL languages, the syntax for the connections is consistent. It is also important to notice that the ports pane is used here to connect to HDL signals that are not actually ports at the top-level module. In fact, connections can be made to signals at any level of the HDL hierarchy by the HDL Verifier cosimulation block.
Languages used for the implementations of the HDL blocks:
top-level (manchester): Verilog
iq converter: VHDL
state counter: VHDL
The actual VHDL and Verilog code will run in the Incisive simulator and its execution will be seen in Simulink as the behavior of the HDL Verifier cosimulation block called "Mixed HDL Manchester Receiver."
Open the mixed-language model.
Double-click the HDL Verifier block and select the "Ports" tab to see the signal connection syntax. Observe that most ports are bound to the top-level Verilog instance. However, the "isum" and "qsum" ports are bound to a lower-level VHDL instance.
Follow the steps outlined in the 'Running a Cosimulation' annotation.