This tutorial guides you through the basic steps for setting up an HDL Verifier™ application using Cosimulation Wizard.
Cosimulation Wizard is a Graphical User Interface (GUI) that guides you through the process of setting up cosimulation between MATLAB® or Simulink® and a Hardware Description Language (HDL) simulator. The supported HDL simulators include ModelSim® and Questa® from Mentor Graphics and Cadence Incisive®.
In this tutorial, we use MATLAB and ModelSim to verify a register transfer level (RTL) design of a raised cosine filter written in Verilog. The raised cosine filter is commonly used as a pulse shaping filter in digital communication systems. It produces no inter-symbol interference (ISI) for the input of modulated pulses.
A Verilog testbench is provided to generate the stimulus to the raised cosine filter. To verify the correctness of this HDL implementation, the testbench calls a MATLAB callback function that instantiates a reference model of the raised cosine filter. The testbench compares the output of the reference model to that of the RTL implementation.
The Cosimulation Wizard takes the provided Verilog files as its input. It also collects user input required for setting up cosimulation in each step. At the end of the tutorial, the Cosimulation Wizard generates a MATLAB script that compiles the HDL design, a MATLAB script that launches the HDL simulator for cosimulation, and a template for the MATLAB callback function. After modifying the generated template to implement the behavior of the raised cosine filter, you can verify the correctness of the RTL design.
For full content of this tutorial, please follow this link Tutorial: Cosimulation Wizard for MATLAB Callback Function.