This example guides you through the basic steps for setting up an HDL Verifier™ application using Cosimulation Wizard.
Cosimulation Wizard is a Graphical User Interface (GUI) that guides you through the process of setting up cosimulation between MATLAB® or Simulink® and a Hardware Description Language (HDL) simulator. The supported HDL simulators include ModelSim® and Questa® from Mentor Graphics and Cadence Incisive®.
In this example, we will use Simulink and ModelSim to verify a register transfer level (RTL) design of a raised cosine filter written in Verilog. The raised cosine filter is commonly used as a pulse shaping filter in digital communication systems. It produces no inter-symbol interference (ISI) for the input of modulated pulses.
To verify the correctness of this raised cosine filter, a Simulink testbench is provided. This testbench generates input to the HDL design under test (DUT) and plots the waveforms of both input and output.
The Cosimulation Wizard takes the provided Verilog file of this raised cosine filter as its input. It also collects user input required for setting up cosimulation in each step. At the end of the example, the Cosimulation Wizard generates a Simulink block that represents the HDL design in the Simulink model, a MATLAB script that compiles HDL design, and a MATLAB script that launches the HDL simulator for cosimulation. During simulation, you can watch the input and output waveforms of this HDL filter in Simulink.
For full content of this example, please follow this link Tutorial: Cosimulation Wizard for Simulink.