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Untimed SystemC/TLM Simulation

This example highlights the use of the 'Untimed' timing mode when you generate a SystemC™/TLM component from a Simulink model using the tlmgenerator target for either Simulink Coder or Embedded Coder™.

In Simulink® models, the movement of data between sources and sinks is controlled by signal sample rates and a centralized timing solver. In SystemC/TLM models, interactions between data sinks and sources are controlled by the SystemC simulation kernel and time advances through SC_THREADs cooperatively yielding control to another thread through wait calls.

For untimed SystemC/TLM simulations, the model ignores annotated delays for communication interfaces and processing. In such models, the goal is only to have a simulation that yields correct results by ensuring that initiators and targets can successfully synchronize the movement of data. There is no attempt to evaluate the performance of a deployed system. No simulation time should elapse while in an untimed simulation because the synchronization is completely event based.

For this example we use a Simulink model of a FIR filter as the basis of the SystemC/TLM generation.

Products required to run this demo:

  • MATLAB

  • Simulink

  • Simulink Coder

  • HDL Verifier

  • SystemC 2.3 (inludes the TLM library)

Note: The example includes a code generation build procedure. Simulink does not permit you to build programs in the MATLAB installation area. If necessary, change to a working directory that is not in the MATLAB installation area prior to starting any build.

1. Open the Preconfigured Model

Open the TLM untimed testbench modelTLM untimed testbench model or in the MATLAB command window execute:

  >> openTlmgDemoModel('uttb')

The following model opens in Simulink.

2. Review the TLM Generator Target Configuration Options

In the model window, from the Simulation menu select Model Configuration Parameters... In the Configuration Parameters dialog box, select the TLM Generator view and the tab TLM Testbench and review the testbench settings as shown in the following image. Select the verbose testbench message checkbox to see the full log of initiator/target interaction in the SystemC/TLM simulation. Since this will be thousands of lines, if desired, deselect the option to get a terse log of the SystemC/TLM simulation.

3. Build the Model

In the model window, right-click on the DualFilter block and select C/C++ Code > Build This Subsystem in the context menu to start the TLM component and testbench generationTLM component and testbench generation. Or you can execute the following command in the MATLAB command window:

  >> buildTlmgDemoModel('uttb')

The generation is completed when the following message appears in the MATLAB command window:

### Starting Simulink Coder build procedure for model: DualFilter
### Successful completion of Simulink Coder build procedure for model: DualFilter

4. Open the Generated Files

Open the generated testbench source code in the MATLAB web browser by clicking on 'DualFilter_uttb_tlm_tb.cpp' in the generated report or in the MATLAB Editor:

5. Review the Generated Code

The specification of 'Without timing' results in the testbench instructing the TLM component to run in untimed mode by means of a special configuration interface, mw_backdoorcfg_IF. As the code indicates, the choice of timing mode is dynamic and can be changed during the course of simulation. Since this choice is purely a simulation construct, it is not programmed by means of a "front-door" TLM transaction.

Additionally, as the code indicates, the testbench must setup a local helper object with the correct timing mode in order to ensure that its initiator threads use the proper synchronization in the TLM transaction calls.

The implementation of the untimed synchronization class, mw_syncuntimed_tb, in the mw_support_tb.cpp file shows the details of the various synchronization calls used by the initiator threads and the TLM transactions. As previously stated, the calls utilize waits of SC_ZERO_TIME and no delays are allowed to accumulate.

6. Verify the Generated Code

In the Configuration Parameters dialog box, go in TLM Testbench configuration parameter dialog and push the Verify TLM Component button to run the generated testbench in the untimed timing moderun the generated testbench in the untimed timing mode or in the MATLAB command window execute:

  >> verifyTlmgDemoModel('uttb')

This action will:

  • build the generated code

  • run Simulink to capture input stimulus and expected results

  • convert the Simulink data to TLM vectors

  • run the stand-alone SystemC/TLM testbench executable

  • convert the TLM results back to Simulink data

  • perform a data comparison

  • generate a Figure window for any signals that had data mis-compares

7. Review the Execution Log

The option to generate verbose messages was selected in order to see how the testbench initiator threads interact and synchronize with the target. In the untimed simulation, notice how the timestamp stays at '0 s' and all polling and timed waits are zero-sim-time synchronization points.

### Starting component verification
### Checking available compiler.
### Building testbench and TLM component.
### Running Simulink simulation to capture inputs and expected outputs.
### Executing TLM testbench to generate actual outputs.

             SystemC 2.3.0-ASI --- Aug 15 2012 14:40:01
        Copyright (c) 1996-2012 by all Contributors,
        ALL RIGHTS RESERVED

[       0 s] (readerThread) 		## found input field tlmg_in1 at tlmg_tlminvec fieldnum 0
[       0 s] (readerThread) 		## found input field tlmg_in2 at tlmg_tlminvec fieldnum 1
[       0 s] (readerThread) 		## found output field tlmg_out1 at tlmg_tlminvec fieldnum 2
[       0 s] (readerThread) 		## found output field tlmg_out2 at tlmg_tlminvec fieldnum 3
[       0 s] (readerThread) 		## setup 2 input data fields, 2 output data fields
## STARTING SIMULATION
[       0 s] (writerThread) ## Start of vectors from MAT file.  Will display '.' for every 100 vectors played.
[       0 s] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM write transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ## vec     0:
##	 initialized input dataset
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[       0 s] (readerThread) 		##	 (Command/Status reg data value = 0x00112200)
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM write transaction to target component at address 00000000
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ## vec     1:
##	 initialized input dataset
[       0 s] (readerThread) 		##	 TLM write transaction to target component at address 0x000020
[       0 s] (readerThread) 		##	 (Command/Status reg data value = 0x00112200)
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM write transaction to target component at address 00000000
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ## vec     2:
##	 initialized input dataset
[       0 s] (readerThread) 		##	 syncing to interrupt signal for data ready in output buffer...
[       0 s] (readerThread) 		##	...saw interrupt
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM write transaction to target component at address 00000000
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 waiting for explicit amount of time (time = 0 ns + 0 ns).
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[       0 s] (readerThread) 		##	 (Command/Status reg data value = 0x00012204)
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 polling for input and output buffers empty...
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000010
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00012204)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		##	 wrote actual output dataset to MAT file buffer.
[       0 s] (readerThread) 		##	 initialized expected output dataset
[       0 s] (readerThread) 		##	 actual output dataset matched expected output dataset
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 waiting for explicit amount of time (time = 0 ns + 0 ns).
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[       0 s] (readerThread) 		##	 (Command/Status reg data value = 0x00012200)
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00012200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000010
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		##	 wrote actual output dataset to MAT file buffer.
[       0 s] (readerThread) 		##	 initialized expected output dataset
[       0 s] (readerThread) 		##	 actual output dataset matched expected output dataset
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 waiting for explicit amount of time (time = 0 ns + 0 ns).
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[       0 s] (readerThread) 		##	 (Command/Status reg data value = 0x00012200)
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00012200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000010
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 waiting for explicit amount of time (time = 0 ns + 0 ns).
[       0 s] (readerThread) 		##	 wrote actual output dataset to MAT file buffer.
[       0 s] (readerThread) 		##	 initialized expected output dataset
[       0 s] (readerThread) 		##	 actual output dataset matched expected output dataset
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[       0 s] (readerThread) 		##	 (Command/Status reg data value = 0x00112200)
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		##	 syncing to interrupt signal for data ready in output buffer...
[       0 s] (writerThread) ##	...saw polling return expected value. (bitValue=0x00110000, bitMask=0x00110000, masked csr=0x00110000)
[       0 s] (writerThread) ## vec     3:
##	 initialized input dataset
[       0 s] (writerThread) ##	 TLM write transaction to target component at address 00000000
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ## vec     4:
##	 initialized input dataset
[       0 s] (writerThread) ##	 TLM write transaction to target component at address 00000000


<<<<<<<<<<<  SNIP >>>>>>>>>>>>>>

[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00012200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000010
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 waiting for explicit amount of time (time = 0 ns + 0 ns).
[       0 s] (readerThread) 		##	 wrote actual output dataset to MAT file buffer.
[       0 s] (readerThread) 		## end of output vectors in MAT file vectors/tlmg_tlminvec.mat for output number 0
[       0 s] (readerThread) 		## end of output vectors in MAT file vectors/tlmg_tlminvec.mat for output number 1
[       0 s] (readerThread) 		##	 initialized expected output dataset
[       0 s] (readerThread) 		##	 actual output dataset matched expected output dataset
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		##	 TLM read  transaction to target component at address 0x000020
[       0 s] (readerThread) 		##	 (Command/Status reg data value = 0x00112200)
[       0 s] (readerThread) 		##	 syncing to local time offset (delay = 0 ns).
[       0 s] (readerThread) 		## end of output data...Terminating readerThread
[       0 s] (readerThread) 		
#############################################
## END OF VECTORS. PLAYED   501 VECTORS.   ##
## DATA MISCOMPARES     :     0            ##
## TRANSPORT ERRORS     :    NO            ##
## MAT FILE WRITE ERRORS:    NO            ##
#############################################
[       0 s] (readerThread) 		##	 Wrote results MAT file.
[       0 s] (writerThread) ##	...saw polling return expected value. (bitValue=0x00110000, bitMask=0x00110000, masked csr=0x00110000)
[       0 s] (writerThread) ## end of input vectors in MAT file vectors/tlmg_tlminvec.mat for input number 0
[       0 s] (writerThread) ## end of input vectors in MAT file vectors/tlmg_tlminvec.mat for input number 1
[       0 s] (writerThread) ##	 waiting for explicit amount of time (time = 0 ns + 0 ns).
[       0 s] (writerThread) ##	 polling for input and output buffers empty...
[       0 s] (writerThread) ##	 polling for input and output buffers empty...
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	...saw polling return expected value. (bitValue=0x00110000, bitMask=0x00110000, masked csr=0x00110000)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 TLM read  transaction to target component at address 0x000020
[       0 s] (writerThread) ##	 (Command/Status reg data value = 0x00112200)
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ##	 syncing to local time offset (delay = 0 ns).
[       0 s] (writerThread) ## end of data...Terminating initiator thread.
## SIMULATION HAS ENDED
### Comparing expected vs. actual results.
Data successfully compared for signal tlmg_out1.
Data successfully compared for signal tlmg_out2.
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