Verifying Viterbi Decoder Using MATLAB System Object and FPGA-in-the-Loop

This example shows you how to use MATLAB® System objects and FPGA-in-the-Loop to simulate a Viterbi decoder implemented in VHDL on a FPGA.

Set FPGA Design Software Environment

Before using FPGA-in-the-Loop, make sure your system environment is set up properly for accessing FPGA design software. You can use the function hdlsetuptoolpath to add ISE or Quartus II to the system path for the current MATLAB session.

For Xilinx FPGA boards, run

>>hdlsetuptoolpath('ToolName', 'Xilinx ISE', 'ToolPath', 'C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64\ise.exe');

This example assumes that the Xilinx ISE executable is C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64\ise.exe. Substitute with your actual executable if it is different.

For Altera boards, run

>>hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath','C:\altera\11.0\quartus\bin\quartus.exe');

This example assumes that the Altera Quartus II executable is C:\altera\11.0\quartus\bin\quartus.exe. Substitute with your actual executable if it is different.

Copy Viterbi HDL Files

Copy the HDL files for the Viterbi example into your local directory


Launch FilWizard

Launch the FIL Wizard prepopulated with the Viterbi example information. Enter your FPGA board information in the first step, follow every step of the Wizard and generate the FPGA programming file and FIL System object.


Program FPGA

Program the FPGA with the generated programming file. Before continuing, make sure the FIL Wizard has finished the FPGA programming file generation. Also make sure your FPGA board is turned on and connected properly.

### Generating iMPACT command file
### Checking iMPACT tool
### Start loading bitstream "S:\MATLAB\demo00\viterbi_block_fil\viterbi_block_fil.bit"
### Loading bitstream "S:\MATLAB\demo00\viterbi_block_fil\viterbi_block_fil.bit" completed successfully

Set Simulation Parameters and Instantiate Communication System Objects

The following code sets up the simulation parameters and instantiates the system objects that represent the channel encoder, BPSK modulator, AWGN channel, BPSK demodulator, and error rate calculator. Those objects comprise the system around the Viterbi decoder and can be thought of as the test bed for the Viterbi HDL implementation.

EsNo = 0;	% Energy per symbol to noise power spectrum density ratio in dB
FrameSize = 1024;  % Number of bits in each frame

% Convolution Encoder
hConEnc = comm.ConvolutionalEncoder;
% BPSK Modulator
hMod    = comm.BPSKModulator;
% AWGN channel
hChan   = comm.AWGNChannel('NoiseMethod', ...
                           'Signal to noise ratio (Es/No)',...
% BPSK demodulator
hDemod  = comm.BPSKDemodulator('DecisionMethod','Log-likelihood ratio',...
% Error Rate Calculator
hError  = comm.ErrorRate('ComputationDelay',100,'ReceiveDelay', 58);

Instantiate the FPGA-in-the-Loop System Object

viterbi_block_fil is a customized FILSimulation System object, which represents the HDL implementation of the Viterbi decoder running on the FPGA in this simulation system.

hDec    = viterbi_block_fil;

Run the Simulation

This example simulates the BPSK communication system in MATLAB incorporating the Viterbi decoder HDL implementation via the FPGA-in-the-Loop System object. This section of the code calls the processing loop to process the data frame-by-frame with 1024 bits in each data frame.

for counter = 1:20480/FrameSize
    data            = randi([0 1],FrameSize,1);
    encodedData     = step(hConEnc, data);
    modSignal       = step(hMod, encodedData);
    receivedSignal  = step(hChan, modSignal);
    demodSignalSD   = step(hDemod, receivedSignal);
    quantizedValue  = fi(4-demodSignalSD,0,3,0);
    input1          = quantizedValue(1:2:2*FrameSize);
    input2          = quantizedValue(2:2:2*FrameSize);

    % Send/receive 1 frame to/from the HDL viterbi decoder on the FPGA
    [ce_out, receivedBits] = step(hDec,input1, input2);

    errors          = step(hError, data, double(receivedBits));

Display the Bit-Error Rate

The Bit-Error Rate is displayed for the Viterbi decoder.

sprintf('Bit Error Rate is %d\n',errors(1))

% This concludes the "Verifying Viterbi Decoder Using MATLAB System Object
% and FPGA-in-the-Loop" example.
ans =

Bit Error Rate is 5.511269e-03

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