This example uses FPGA-in-the-Loop (FIL) simulation to accelerate a video processing simulation with Simulink® by adding an FPGA. The process shown analyzes a simple system that sharpens an RGB video input at 24 frames per second.
This example uses the Computer Vision System Toolbox™ in conjunction with Simulink® HDL Coder™ and HDL Verifier™ to show a design workflow for implementing FIL simulation.
Products required to run this example:
DSP System Toolbox
Computer Vision System Toolbox
FPGA design software (Xilinx® ISE® or Vivado® design suite or Altera® Quartus® II design software)
One of the supported FPGA development boards and accessories (the ML403, SP601, BeMicro SDK, and Cyclone III Starter Kit boards are not supported for this example)
For connection using Ethernet: Gigabit Ethernet Adapter installed on host computer, Gigabit Ethernet crossover cable
For connection using JTAG: USB Blaster I or II cable and driver for Altera FPGA boards. Digilent® JTAG cable and driver for Xilinx FPGA boards.
For connection using PCI Express®: FPGA board installed into PCI Express slot of host computer.
MATLAB® and FPGA design software can either be locally installed on your computer or on a network accessible device. If you use software from the network you will need a second network adapter installed in your computer to provide a private network to the FPGA development board. Consult the hardware and networking guides for your computer to learn how to install the network adapter.
Note: The demonstration includes code generation. Simulink does not permit you to modify the MATLAB installation area. If necessary, change to a working directory that is not in the MATLAB installation area prior to starting this example.
Open the fil_videosharp_sim.mdl and run the simulation for 0.21s.
Due to the large quantity of data to process , the simulation is not fluent. We will improve the simulation speed in the following steps by using a FPGA-in-the-Loop.
Generate HDL code for the Streaming Video Sharpening subsystem by performing these steps:
a. Right-click on the block labeled
Streaming 2-D FIR Filter.
b. Select HDL Code Generation > Generate HDL for Subsystem in the context menu.
Alternatively, you can generate HDL code by entering the following command at the MATLAB prompt:
>> makehdl('fil_videosharp_sim/Streaming 2-D FIR Filter')
If you do not want to generate HDL code, you can copy pre-generated HDL files to the current directory using this command:
Before using FPGA-in-the-Loop, make sure your system environment is set up properly for accessing FPGA design software. You can use the function hdlsetuptoolpath to add ISE or Quartus II to the system path for the current MATLAB session.
For Xilinx FPGA boards, run
hdlsetuptoolpath('ToolName', 'Xilinx ISE', 'ToolPath', 'C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64\ise.exe');
This example assumes that the Xilinx ISE executable is C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64\ise.exe. Substitute with your actual executable if it is different.
For Altera boards, run
hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath','C:\altera\11.0\quartus\bin\quartus.exe');
This example assumes that the Altera Quartus II executable is C:\altera\11.0\quartus\bin\quartus.exe. Substitute with your actual executable if it is different.
To launch the FIL Wizard, select Tools > Verification Wizards > FPGA-in-the-Loop (FIL)... in the model window or enter the following command at the MATLAB prompt:
Select a board in the board list.
a. Add the previously generated HDL source files for the
Streaming Video Sharpening subsystem.
Streaming_2_D_FIR_Filter.vhd as the Top-level file.
Do not change anything in this view.
a. Select an output folder.
b. Click Build to build the FIL block and the FPGA programming file.
During the build process, the following actions occur:
A FIL block named Streaming_2_D_FIR_Filter is generated in a new model. Do not close this model.
After new model generation, the FIL Wizard opens a command window where the FPGA design software performs synthesis, fit, place-and-route, timing analysis, and FPGA programming file generation. When the FPGA design software process is finished, a message in the command window lets you know you can close the window. Close the window.
c. Close the fil_videosharp_sim model.
a. Open the fil_videosharp_fpga.mdl.
b. Copy in it the previously generated FIL block to fil_videosharp_fpga.mdl where it say "Replace this with FIL block"
a. Double-click the FIL block in the Streaming Video Sharpening with FPGA-in-the-Loop model to open the block mask.
b. Click Load.
c. Click OK to close the block mask.
Run the simulation for 10s and observe the performance improvement.
This concludes the Video Processing Acceleration using FPGA-In-the-Loop example.