Before you can use FPGA-in-the-loop (FIL) simulation, you must download the support package for your board. See Download FPGA Board Support Package. Alternatively, you can manually create custom board definition files for use with FIL simulation. See FPGA Board Customization.
|FPGA-in-the-Loop Wizard||Generate an FPGA-in-the-loop (FIL) block or System object from existing HDL files|
||Construct System object for FIL simulation with MATLAB|
|FIL Simulation||Simulate HDL code on FPGA hardware from Simulink|
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink® or MATLAB® software for testing designs in real hardware for any existing HDL code.
The FPGA board support packages contain the definition files for all the supported boards for FPGA-in-the-loop (FIL) simulation.
Set the MATLAB path to Xilinx® and Altera® software.
Describes the steps in the automated support package setup process for configuring hardware for use with FPGA-in-the-loop.
Describes the steps necessary to prep hardware and hardware tools for FIL
DUT guidelines for FIL simulation of blocks and System objects.
Generate a FPGA-in-the-Loop block from existing HDL source files, then include the FPGA implementation in a Simulink simulation.
Generate a FPGA-in-the-Loop System object from existing HDL source files, then include the FPGA implementation in a MATLAB simulation
This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.
This example shows you how to verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.
Follow instructions for invoking the HDL Workflow Advisor in MATLAB.
How to generate test bench and code coverage for your HDL code using the HDL Workflow Advisor
Follow instructions for invoking the HDL Workflow Advisor.
If you get a message or error at any time during the FIL process (from generating the FIL block to running the simulation), consult one of the following tables for a possible reason and solution.