Documentation

FPGA-in-the-Loop

Test designs in real hardware

Before you can use FPGA-in-the-loop (FIL) simulation, you must download the support package for your board. See Download FPGA Board Support Package. Alternatively, you can manually create custom board definition files for use with FIL simulation. See FPGA Board Customization.

After you download a board support package, select a simulation workflow. See FPGA-in-the-Loop Simulation Workflows. To learn how FIL simulation works, see FPGA-in-the-Loop Simulation.

Functions

filWizard Run FPGA-in-the-Loop Wizard

System Objects

hdlverifier.FILSimulation Construct System object for FIL simulation with MATLAB

Blocks

FIL Simulation Simulate HDL code on FPGA hardware from Simulink

Examples and How To

FIL Preparation

Download FPGA Board Support Package

The FPGA board support packages contain the definition files for all the supported boards for FPGA-in-the-loop (FIL) simulation.

Set Up FPGA Design Software Tools

Set the MATLAB® path to Xilinx® and Altera® software.

Guided Hardware Setup

Describes the steps in the automated support package setup process for configuring hardware for use with FPGA-in-the-loop.

Manual Hardware Setup

Describes the steps necessary to prep hardware and hardware tools for FIL

Prepare DUT For FIL Interface Generation

DUT guidelines for FIL simulation of blocks and System objects.

Generate FIL Interface from Legacy Code

Block Generation with the FIL Wizard

Generate a FPGA-in-the-Loop block from existing HDL source files.

System Object Generation with the FIL Wizard

Generate a FPGA-in-the-Loop System object™ from existing HDL source files.

Perform FPGA-in-the-Loop Simulation

Run FPGA-in-the-loop simulation using the block or object you created.

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop

This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.

Verify Digital Up-Converter Using FPGA-in-the-Loop

This example shows you how to verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.

Generate FIL System Object from MATLAB Code

FIL Simulation with HDL Workflow Advisor for MATLAB

Follow instructions for invoking the HDL Workflow Advisor in MATLAB.

Generate FIL Block from Simulink Model

FIL Simulation with HDL Workflow Advisor for Simulink

Follow instructions for invoking the HDL Workflow Advisor.

Concepts

FPGA-in-the-Loop Simulation Workflows

Choose between generating a block or System object, and decide whether to use the FIL Wizard or HDL Workflow Advisor.

FPGA-in-the-Loop Simulation

FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink® or MATLAB software for testing designs in real hardware for any existing HDL code.

Troubleshooting

Troubleshooting FIL

If you get a message or error at any time during the FIL process (from generating the FIL block to running the simulation), consult one of the following tables for a possible reason and solution.

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