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Getting Started with HDL Verifier


HDL Cosimulation

Verify HDL Module with MATLAB Test Bench

Set up and run a ModelSim® and MATLAB® test bench session.

Verify HDL Module with Simulink Test Bench

The steps for setting up an HDL Verifier™ session that uses Simulink® to verify a simple VHDL® model.

HDL Code Import

Cosimulation Wizard for MATLAB System Object

This example guides you through the basic steps for setting up an HDL Verifier™ application using the Cosimulation Wizard.

Verify Raised Cosine Filter Design Using Simulink

Provides instruction in using the Cosimulation Wizard to create a Simulink model for cosimulation

TLM Component Generation

Getting Started with TLM Generator

This example shows how to configure a Simulink® model to generate a SystemC™/TLM component using the tlmgenerator target for either Simulink Coder or Embedded Coder™.

FPGA-in-the-Loop (FIL)

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop

This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.

Verify Digital Up-Converter Using FPGA-in-the-Loop

This example shows you how to verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.

Verify Generated HDL Code with HDL Workflow Advisor (requires HDL Coder license)

Choose a Test Bench for Generated HDL Code (HDL Coder)

Select between generated test bench options.

Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)

How to generate test bench and code coverage for your HDL code using the HDL Workflow Advisor

Design Verification Automation

HDL Cosimulation

The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.

FPGA Verification

HDL Verifier™ works with Simulink or MATLAB and HDL Coder™ and the supported FPGA development environment to prepare your automatically generated HDL code for implementation in an FPGA.

TLM Component Generation

HDL Verifier lets you create a SystemC Transaction Level Model (TLM) that can be executed in any OSCI-compatible TLM 2.0 environment, including a commercial virtual platform.

SystemVerilog DPI Component Generation

HDL Verifier works with Simulink Coder™ or MATLAB Coder to export a subsystem as generated C code inside a SystemVerilog component with a Direct Programming Interface (DPI).

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