HDL Verifier™ automatically generates test benches for Verilog® and VHDL® design verification. You can use MATLAB® or Simulink® to directly stimulate your design and then analyze its response using HDL cosimulation or FPGA-in-the-loop with Xilinx® and Altera® FPGA boards. This approach eliminates the need to author standalone Verilog or VHDL test benches.
HDL Verifier also generates components that reuse MATLAB and Simulink models natively in simulators from Cadence®, Mentor Graphics®, and Synopsys®. These components can be used as verification checker models or as stimuli in more complex test-bench environments such as those that use the Universal Verification Methodology (UVM).
Cosimulation with Cadence Incisive®, Mentor Graphics® ModelSim®, or Questa®
FPGA-in-the-loop verification using Xilinx and Altera FPGA boards
SystemVerilog DPI component generation from MATLAB functions and Simulink blocks
Generation of IEEE® 1666 SystemC TLM 2.0 compatible transaction-level models
Automated verification workflow with HDL Coder™