HDL Verifier™ automates Verilog® and VHDL® design verification using HDL simulators and FPGA hardware-in-the-loop. It provides interfaces that link MATLAB® and Simulink® with Cadence Incisive®, Mentor Graphics® ModelSim®, and Mentor Graphics Questa® HDL simulators. It also supports FPGA-in-the-loop verification with Xilinx® and Altera® FPGA boards.
HDL Verifier automates verification by using MATLAB or Simulink to stimulate your HDL code and analyze its response. This approach eliminates the need to author standalone Verilog or VHDL test benches.
Cosimulation support for Cadence Incisive and for Mentor Graphics ModelSim and Questa
FPGA-in-the-loop verification using Xilinx and Altera FPGA boards
MATLAB functions and Simulink blocks
Generation of IEEE® 1666 SystemC TLM 2.0 compatible transaction-level models
Interactive or batch-mode cosimulation and debugging
Single-machine, multiple-machine, and cross-network cosimulation