Documentation

HDL Verifier

Verify VHDL and Verilog using HDL simulators and FPGA-in-the-loop test benches

HDL Verifier™ automates Verilog® and VHDL® design verification using HDL simulators and FPGA hardware-in-the-loop. It provides interfaces that link MATLAB® and Simulink® with Cadence Incisive®, Mentor Graphics® ModelSim®, and Mentor Graphics Questa® HDL simulators. It also supports FPGA-in-the-loop verification with Xilinx® and Altera® FPGA boards.

HDL Verifier automates verification by using MATLAB or Simulink to stimulate your HDL code and analyze its response. This approach eliminates the need to author standalone Verilog or VHDL test benches.

Verification with Cosimulation

Cosimulation between HDL simulators and MATLAB and Simulink

Verification with FPGA Hardware

FPGA-in-the-Loop verification with MATLAB and Simulink

Transaction Level Model Generation

Generation of SystemC TLM virtual prototypes

SystemVerilog DPI Component Generation

Generation of SystemVerilog direct programming interface (DPI) components

Supported Hardware

Support for third-party hardware, such as Xilinx and Altera FPGA boards