HDL Verifier™ automates Verilog® and VHDL® design verification using HDL simulators and FPGA hardware-in-the-loop. It provides interfaces that link MATLAB® and Simulink® with Cadence Incisive®, Mentor Graphics® ModelSim®, and Mentor Graphics Questa® HDL simulators. It also supports FPGA-in-the-loop verification with Xilinx® and Altera® FPGA boards.
HDL Verifier automates verification by using MATLAB or Simulink to stimulate your HDL code and analyze its response. This approach eliminates the need to author standalone Verilog or VHDL test benches.
Cosimulation between HDL simulators and MATLAB and Simulink
FPGA-in-the-Loop verification with MATLAB and Simulink
Generation of SystemC TLM virtual prototypes
Generation of SystemVerilog direct programming interface (DPI) components
Support for third-party hardware, such as Xilinx and Altera FPGA boards