Simulate HDL code on FPGA hardware from Simulink
Example of FIL Block Generated From HDL Code
The generated FIL simulation block is the communication interface between the FPGA and your Simulink® model. It integrates the hardware into the simulation loop and allows it to participate in simulation as any other block.
You can perform FIL simulation with the instructions found in Perform FPGA-in-the-Loop Simulation. If you encounter any issues during FIL simulation, refer to Troubleshooting FIL for help in diagnosing the problem.
You can use the FIL Simulation block in models running in Normal, Accelerator, or Rapid Accelerator simulation modes. The FIL Simulation parameters are not tunable in any of the simulation modes. For more information about these modes, see How Acceleration Modes Work in the Simulink User's Guide.
Use the FIL block mask to perform the following tasks:
Download the generated FPGA programming file onto the FPGA. You must perform this step before you can run a FIL simulation. See Load Programming File onto FPGA.
Example of FIL Block Mask Main Tab (Generated From HDL Code)
On the Main tab, you have the following options and information:
Connection: Either Ethernet or PCI Express®. Some boards can use only one connection type or the other; with other boards, you may have the option of using either connection.
Board: The board you selected in the FPGA-in-the-Loop Wizard.
FPGA part: Chip identification number
FPGA project file: The name of the Xilinx® project file that was created with the FPGA-in-the-Loop Wizard.
FPGA Programming File
This option is how you download the FPGA programming file. You can verify that the file name in FPGA programming file name is as you expected; if it is not, you can change it here. If you have no other changes to the block mask, click Load to initiate the download.
Change HDL overclocking factor for the current FIL simulation.
This setting specifies that an input value is sampled x times
by the FPGA clock before the input changes value, where x is
the value you entered in this field. Select
auto or enter an expression, variable, or function.
Output frame size
Change the output frame size for the current FIL simulation.
Specify the output frame size as an expression, variable, or function,
Example of FIL Block Mask Signal Attributes Tab (Generated From HDL Code)
On the Signal Attributes tab, you have the following options:
Change output sample times.
You may explicitly set sample times or use
internal rule. The internal rule is to set the output
sample times to the input base sample time divided by the scaling
Change output data types.
You may explicitly set data types, use the default of an unscaled
and unsigned data type, or specify
Inherit: auto to
inherit a data type from the block's context.