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# HDL Cosimulation

Cosimulate hardware component by communicating with HDL module instance executing in HDL simulator

• Library:
• HDL Verifier / For Use with Mentor Graphics Modelsim

HDL Verifier / For Use with Cadence Incisive

## Description

The HDL Cosimulation block cosimulates a hardware component by applying input signals to and reading output signals from an HDL model under simulation in the HDL simulator. You can use this block to model a source or sink device by configuring the block with input or output ports only.

You can configure these options on the block:

• Map the input and output ports of the block to correspond with signals (including internal signals) of an HDL module. You must specify a sample time for each output port; you can optionally specify a data type for each output port.

• Type of communication and communication settings used to exchange data between simulators.

• The timing relationship between units of simulation time in Simulink® and the HDL simulator.

• Rising-edge or falling-edge clocks to apply to your model. You can specify the period for each clock signal.

• Tcl commands to run before and after the simulation.

 Compatibility with Simulink Code Generation   HDL Coder™: The HDL Verifier™ HDL Cosimulation block does participate in code generation with HDL Coder.Simulink Coder™: The HDL Verifier HDL Cosimulation block does not participate in code generation with Simulink Coder for C code generation.

## Ports

The ports shown on the block correspond with signals from your HDL design running in the HDL simulator. You can add and remove ports, and configure their data types and sample times, by changing the block parameters. The Ports parameter group displays the HDL signals that correspond to the ports. You can add, remove, and change the order of the ports. Use the Auto Fill button to fill the table via a port information request to the HDL simulator. This request returns port names and information from your HDL design running in the HDL simulator. See "Get Signal Information from HDL Simulator" for a detailed description of this feature.

 Note:   All signals you specify when you configure the HDL Cosimulation block must have read/write access in the HDL simulator. Refer to the HDL simulator product documentation for details.
 Note:   When you import VHDL® signals from the HDL simulator, HDL Verifier returns the signal names in all capitals.

## Parameters

expand all

### Ports

Eliminates the one output-sample delay difference between the cosimulation and Simulink that occurs when your model contains purely combinational paths. Clear this check box if the HDL Cosimulation block is in a feedback loop and generates algebraic loop warnings/errors. When you simulate a sequential circuit that has a register on the datapath, specifying direct feedthrough does not affect the timing of that datapath.

Signal path name, using the HDL simulator path name syntax. For example (for use with Incisive®), `manchester.samp`. The signal can be at any level of the HDL design hierarchy. The HDL Cosimulation block port corresponding to the signal is labeled with this name.

For rules on specifying signal/port and module path specifications in Simulink, see "Specify HDL Signal/Port and Module Paths for Cosimulation".

 Copying Signal Path Names   You can copy signal path names directly from the HDL simulator wave window and paste them into the Full HDL Name field. Use the `Path.Name` view and not Db::Path.Name view. After pasting a signal path name into the Full HDL Name field, click the Apply button to complete the paste operation and update the signal list.

Select either `Input`, `Output`. To add a bidirectional port, add the port to the list twice, as both input and output.

`Input` — HDL signals that Simulink drives. Simulink deposits values on the specified the HDL simulator signal at the specified sample rate.

 Note:   When you define a block input port, make sure that only one source is set up to drive input to that signal. For example, avoid defining an input port that has multiple instances. If multiple sources drive input to a single signal, your simulation model produces unexpected results.

`Output` — HDL signals that Simulink reads. For output signals, you must specify an explicit sample time. You can also specify the data type, but the width must match the width of the signal in HDL. For details on specifying a data type, see Data Type and Fraction Length.

Simulink signals do not have the semantic of tri-states (there is no 'Z' value). To interface with bidirectional signals, connect to the input and enable signals of the output driver, and the output signal of the input driver. This approach leaves the actual tri-state buffer in HDL where resolution functions can handle interfacing with other tri-state buffers.

Time interval between consecutive samples applied to the output port. This parameter applies only to signals marked as `Output`.

Simulink deposits an input port signal on an HDL simulator signal at the specified sample rate. Conversely, Simulink reads an output port signal from a specified HDL simulator signal at the specified sample rate.

In general, Simulink handles port sample periods as follows:

• If you connect an input port to a signal that has an explicit sample period, based on forward propagation, Simulink applies that rate to the port.

• If you connect an input port to a signal that does not have an explicit sample period, Simulink assigns a sample period that is equal to the least common multiple (LCM) of all identified input port sample periods in the model.

• After Simulink sets the input port sample periods, it applies user-specified output sample times to all output ports. You must specify an explicit sample time for each output port.

The exact interpretation of the output port sample time depends on the settings of the Timescales parameters of the HDL Cosimulation block. See also Simulation Timescales.

Select `Inherit` to direct Simulink to determine the data type. Simulink checks that the inherited word length matches the word length queried from the HDL simulator. If they do not match, Simulink generates an error message. For example, if you connect a Signal Specification block to an output, Simulink forces the data type specified by the Signal Specification block on the output port.

If Simulink cannot determine the data type of the signal connected to the output port, it queries the HDL simulator for the data type of the port. As an example, if the HDL simulator returns the VHDL data type `STD_LOGIC_VECTOR` for a signal of size `N` bits, the data type `ufixN` is forced on the output port. The implicit fraction length is 0.

You can also assign an explicit data type (with optional Fraction Length). By explicitly assigning a data type, you can force fixed-point data types on output ports of the HDL Cosimulation block. For example, for an 8-bit output port, setting the Data Type to `Signed` and setting the Fraction Length to `5` forces the data type to `sfix8_En5`. You cannot force width; the width is always inherited from the HDL simulator.

 Note:   The Data Type and Fraction Length properties apply only to the following types of HDL signals:VHDL signals of any logic type, such as`STD_LOGIC` or `STD_LOGIC_VECTOR`Verilog® signals of `wire` or `reg` type

Sign designation for explicit data types. This parameter applies when you set Data Type to `Fixedpoint`

Size, in bits, of the fractional part of the signal in fixed-point representation. Fraction Length becomes available if you do not set the Data Type property to `Inherit`. For example, for an 8-bit output port, setting the Data Type to `Signed` and setting the Fraction Length to `5` forces the data type to `sfix8_En5`. You cannot force width; the width is always inherited from the HDL simulator.

 Note:   The Data Type and Fraction Length properties apply only to the following types of HDL signals:VHDL signals of any logic type, such as`STD_LOGIC` or `STD_LOGIC_VECTOR`Verilog signals of `wire` or `reg` type

### Clocks

Create optional rising-edge and falling-edge clocks that apply stimuli to your cosimulation model. The scrolling list displays HDL clocks that drive values to the HDL signals that you are modeling, using the deposit method. The clock signals must be single-bit signals, vector signals are not supported. For instructions on adding and editing clock signals, see Creating Optional Clocks with the Clocks Pane of the HDL Cosimulation Block.

Specify each clock as a signal path name, using the HDL simulator path name syntax. For example: `/manchester/clk` or `manchester.clk`.

For information about and requirements for path specifications in Simulink, see "Specify HDL Signal/Port and Module Paths for Cosimulation".

 Note:   You can copy signal path names directly from the HDL simulator wave window and paste them into the Full HDL Name field. Use the `Path.Name` view, not the `Db::Path.Name` view. After pasting a signal path name into the Full HDL Name field, click the Apply button to complete the paste operation and update the signal list.

Select `Rising` or `Falling` to specify either a rising-edge clock or a falling-edge clock.

You must either specify the clock period explicitly or accept the default period of `2`.

To specify an explicit clock period, enter a sample time equal to or greater than two resolution units (ticks).

If the clock period is not an even integer, Simulink cannot create a 50% duty cycle. Instead, the HDL Verifier software creates the falling edge at

`$clockperiod/2$`

(rounded down to the nearest integer).

### Timescales

Choose a timing relationship between Simulink and the HDL simulator, either manually or automatically. These parameters specify a correspondence between one second of Simulink time and some quantity of HDL simulator time. This quantity of HDL simulator time can be expressed in one of the following ways:

• Relative timing relationship (Simulink seconds correspond to an HDL simulator-defined tick interval)

• Absolute timing relationship (Simulink seconds correspond to an absolute unit of HDL simulator time)

For more information on calculating relative and absolute timing modes, see Defining the Simulink and HDL Simulator Timing Relationship.

For detailed information on the relationship between Simulink and the HDL simulator during cosimulation, and on the operation of relative and absolute timing modes, see Simulation Timescales.

If you select this option, HDL Verifier calculates the timescale when you start the Simulink simulation. If this option is not selected, use the Determine Timescale Now button to calculate the timescale immediately without starting a simulation, or manually select a timescale. For guidance through the automatic timescale calculation, see Automatically Specifying the Timing Relationship.

This parameter consists of a Time value and a TimeUnit value.

 Specify a Relative Timing Relationship   To configure relative timing mode for a cosimulation, perform the following steps:Verify that `Tick`, the default setting for TimeUnit, is selected. If it is not, then select it from the list on the right.Enter a scale factor in the Time text box on the left. The default scale factor is 1.
 Specify an Absolute Timing Relationship   To configure absolute timing mode for a cosimulation, perform the following steps:Select a unit of absolute time from the TimeUnit list on the right. The units available include `fs` (femtoseconds), `ps` (picoseconds), `ns` (nanoseconds), `us` (microseconds), `ms` (milliseconds), and `s` (seconds).Enter a scale factor in the Time text box on the left. The default scale factor is 1.

### Connection

Type of connection between the HDL simulator and Simulink. When you select the second and third options, the cosimulation interface does not communicate with the HDL simulator during Simulink simulation.

• `Full Simulation`: Confirm interface and run HDL simulation.

• `Confirm Interface Only`: Connect to the HDL simulator and check for signal names, dimensions, and data types, but do not run HDL simulation.

• `No Connection`: Do not communicate with the HDL simulator. The HDL simulator does not need to be started.

When both applications run on the same computer, you can choose shared memory or TCP sockets for the communication channel between the applications. If you do not select this option, only TCP/IP socket mode is available, and the Connection method list becomes unavailable.

This list becomes available when you select HDL Simulator is running on this computer.

• `Socket`: Simulink and the HDL simulator communicate via a designated TCP/IP socket. TCP/IP socket mode is more versatile. You can use it for single-system and network configurations. This option offers the greatest scalability. For more on TCP/IP socket communication, seeTCP/IP Socket Ports.

• `Shared memory`: Simulink and the HDL simulator communicate via shared memory. Shared memory communication provides optimal performance

and is the default mode of communication.

This parameter applies if you run Simulink and the HDL simulator on different computers.

Indicate a valid TCP socket port number or service for your computer system (if not using shared memory). For information on choosing TCP socket ports, see TCP/IP Socket Ports.

When you select this option, the HDL Cosimulation block icon displays the current communication parameter settings. If you select shared memory, the icon displays `SharedMem`. If you select TCP socket communication, the icon displays `Socket` and displays the host name and port number in the format `hostname:port`.

This information can help distinguish between multiple HDL Cosimulation blocks, where each block is communicating to a different instance of the HDL simulator.

### Simulation

Specifies the amount of time to run the HDL simulator before beginning simulation in Simulink. Specifying this time properly aligns the signal of the Simulink block and the HDL signal so that they can be compared and verified directly without additional delays.

This setting consists of a PreRunTime value and a PreRunTimeUnit value.

• PreRunTime: Any valid time value. The default is 0.

• PreRunTimeUnit: Specifies the units of time for PreRunTime.

• `Tick`

• `s`

• `ms`

• `us`

• `ns`

• `ps`

• `fs`

The cosimulation tool executes these commands in the HDL simulator, before simulating the HDL component of your Simulink model. If you enter multiple commands on one line, append each command with a semicolon (;), the standard Tcl concatenation operator.

For example, use this parameter to generate a one-line echo command to confirm that a simulation is running, or a complex script that performs an extensive simulation initialization and startup sequence. You cannot use these commands to change simulation state.

You can specify any valid Tcl command. The Tcl command you specify cannot include commands that load an HDL simulator project or modify simulator state. For example, the character vector cannot include commands such as `start`, `stop`, or `restart` (for ModelSim®) or `run`, `stop`, or `reset` (for Incisive).

The cosimulation tool executes these commands in the HDL simulator, after simulating the HDL component of your Simulink model.

You can specify any valid Tcl command. The Tcl command you specify cannot include commands that load an HDL simulator project or modify simulator state. For example, the character vector cannot include commands such as `start`, `stop`, or `restart` (for ModelSim) or `run`, `stop`, or `reset` (for Incisive).

 Note for ModelSim Users   After each simulation, it takes ModelSim time to update the coverage result. To prevent the potential conflict between this process and the next cosimulation session, add a short pause between each successive simulation.

### Automatically Specifying the Timing Relationship

To have the HDL Verifier software calculate the timing relationship for you, perform the following steps:

1. Verify that the HDL simulator is running. HDL Verifier software can obtain the resolution limit of the HDL simulator only when that simulator is running.

2. Choose to have HDL Verifier software suggest a timescale, immediately, or calculate the timescale when you start the Simulink simulation.

• To have the calculation performed while you are configuring the block, click the Timescale pane, and then click Determine Timescale Now. The software connects Simulink with the HDL simulator so that Simulink can use the HDL simulator resolution to calculate the best timescale. The link then displays those results to you in the Timescale Details dialog box.

 Note:   For the results to display, make sure that the HDL simulator is running and the design is loaded for cosimulation. The simulation does not have to be running.

You can accept the timescale the software suggests, or you can change the port list directly:

• If you want to revert to the originally calculated settings, click Use Suggested Timescale.

• If you want to view sample times for all ports in the HDL design, select Show all ports and clocks.

• To have the calculation performed when the simulation begins, select Automatically determine timescale at start of simulation, and click Apply. You obtain the same Timescale Details dialog box when the simulation starts in Simulink.

 Note:   For the results to display, make sure that the HDL simulator is running and the design loaded for cosimulation. The simulation does not have to be running.

HDL Verifier software analyzes all the clock and port signal rates from the HDL Cosimulation block when the software calculates the scale factor.

 Note:   HDL Verifier software cannot automatically calculate a sample timescale based on any signals driven via Tcl commands or in the HDL simulator. The link software cannot perform such calculations because it cannot know the rates of these signals.

The link software returns the sample rate in either seconds or ticks:

• If the results are in seconds, then the link software was able to resolve the timing differences in favor of fidelity (absolute time).

• If the results are in ticks, then the link software was best able to resolve the timing differences in favor of efficiency (relative time).

Each time you select Determine Timescale Now or Automatically determine timescale at start of simulation, the HDL Verifier software opens an interactive display. This display explains the results of the timescale calculations. If the link software cannot calculate a timescale for the given sample times, adjust your sample times in the Port List.

3. Click Apply to commit your changes.

 Note:   HDL Verifier does not support timescales calculated automatically from frame-based signals.

### Set Parameters from a Tcl Script

You can create a Tcl script that lists the Tcl commands you want to execute on the HDL simulator, either pre- or post-simulation.

#### Tcl Scripts for ModelSim Users

You can create a ModelSim DO file that lists Tcl commands and then specify that file with the ModelSim `do` command as follows:

```do mycosimstartup.do ```

Or

```do mycosimcleanup.do ```

You can include the `quit -f` command in an after-simulation Tcl command or DO file to force ModelSim to shut down at the end of a cosimulation session. Specify all after simulation Tcl commands in a single cosimulation block and place `quit` at the end of the command or DO file.

Except for `quit`, the command or DO file that you specify cannot include commands that load a ModelSim project or modify simulator state. For example, they cannot include commands such as `start`, `stop`, or `restart`.

#### Tcl Scripts for Incisive Users

You can create an HDL simulator Tcl script that lists Tcl commands and then specify that file with the HDL simulator `source` command as follows:

```source mycosimstartup.script_extension ```

Or

```source mycosimcleanup.script_extension ```

You can include the `exit` command in an after-simulation Tcl script to force the HDL simulator to shut down at the end of a cosimulation session. Specify all after simulation Tcl commands in a single cosimulation block and place `exit` at the end of the command or Tcl script.

Except for `exit`, the command or Tcl script that you specify cannot include commands that load an HDL simulator project or modify simulator state. For example, they cannot include commands such as `run`, `stop`, or `reset`.

The following example shows a Tcl script when the `-gui` argument was used with `hdlsimmatlab` or `hdlsimulink`:

`after 1000 {ncsim -submit exit}`

This next example is of a Tcl exit script to use when the `-tcl` argument was used with `hdlsimmatlab` or `hdlsimulink`:

`after 1000 {exit}`

#### Introduced in R2008a

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