Documentation

HDL Cosimulation

Cosimulate hardware component by communicating with HDL module instance executing in HDL simulator

Library

HDL Verifier

Description

The HDL Cosimulation block cosimulates a hardware component by applying input signals to and reading output signals from an HDL model under simulation in the HDL simulator. You can use this block to model a source or sink device by configuring the block with input or output ports only.

The tabbed panes on the block's dialog box let you configure:

  • Block input and output ports that correspond to signals (including internal signals) of an HDL module. You must specify a sample time for each output port; you can also specify a data type for each output port.

  • Type of communication and communication settings used to exchange data between simulators.

  • The timing relationship between units of simulation time in Simulink® and the HDL simulator.

  • Rising-edge or falling-edge clocks to apply to your model. You can specify the period for each clock signal.

  • Tcl commands to run before and after the simulation.

    Compatibility with Simulink Code Generation  

    • HDL Coder™: The HDL Verifier™ HDL Cosimulation block does participate in code generation with HDL Coder.

    • Simulink Coder™: The HDL Verifier HDL Cosimulation block does not participate in code generation with Simulink Coder for C code generation.

The HDL Cosimulation Block Panes

The Ports pane provides fields for mapping signals of your HDL design to input and output ports in your block. The signals can be at any level of the HDL design hierarchy.

The Timescales pane lets you choose an optimal timing relationship between Simulink and the HDL simulator. You can configure either of the following timing relationships:

  • Relative timing relationship (Simulink seconds correspond to an HDL simulator-defined tick interval)

  • Absolute timing relationship (Simulink seconds correspond to an absolute unit of HDL simulator time)

The Connection pane specifies the communications mode used between Simulink and the HDL simulator. If you use TCP socket communication, this pane provides fields for specifying a socket port and for the host name of a remote computer running the HDL simulator. The Connection pane also provides the option for bypassing the cosimulation block during Simulink simulation.

The Clocks pane lets you create optional rising-edge and falling-edge clocks that apply stimuli to your cosimulation model.

The Simulation pane provides a way of specifying tools command language (Tcl) commands to be executed before and after the HDL simulator simulates the HDL component of your Simulink model. You can use the Pre-simulation commands field on this pane for simulation initialization and startup operations, but you cannot use it to change simulation state.

    Note:   You must make sure that signals being used in cosimulation have read/write access. This rule applies to all signals on the Ports, Clocks, and Simulation panes. Verify such access through the HDL simulator—see product documentation for details.

Dialog Box

The Block Parameters dialog box consists of the following tabbed panes of configuration options:

Ports Pane

Specify fields for mapping signals of your HDL design to input and output ports in your block. Simulink deposits an input port signal on an HDL simulator signal at the signal's sample rate. Conversely, Simulink reads an output port signal from a specified HDL simulator signal at the specified sample rate.

In general, Simulink handles port sample periods as follows:

  • If you connect an input port to a signal that has an explicit sample period, based on forward propagation, Simulink applies that rate to the port.

  • If you connect an input port to a signal that does not have an explicit sample period, Simulink assigns a sample period that is equal to the least common multiple (LCM) of all identified input port sample periods for the model.

  • After Simulink sets the input port sample periods, it applies user-specified output sample times to all output ports. You must specify an explicit sample time for each output port.

In addition to specifying output port sample times, you can force the fixed-point data types on output ports. For example, setting the Data Type property of an 8-bit output port to Signed and setting its Fraction Length property to 5 would force the data type to sfix8_En5. You can not force width; the width is always inherited from the HDL simulator.

    Note:   The Data Type and Fraction Length properties apply only to the following signals:

    • VHDL signals of any logic type, such asSTD_LOGIC or STD_LOGIC_VECTOR

    • Verilog signals of wire or reg type

You can set input/output ports in the Ports pane also. To do so, specify port as both input and output (example shown for use with ModelSim®).

The Enable direct feedthrough option eliminates the one output-sample delay difference between the cosimulation and Simulink that occurs when your model contains purely combinational paths. Clear this check box if the cosimulation block is in a feedback loop and generates algebraic loop warnings/errors. When you simulate a sequential circuit that has a register on the datapath, specifying direct feedthrough does not affect the timing of that datapath.

The list at the center of the pane displays HDL signals corresponding to ports on the HDL Cosimulation block. Maintain this list with the buttons on the left of the pane:

  • Auto Fill — Transmit a port information request to the HDL simulator. The port information request returns port names and information from an HDL model (or module) under simulation in the HDL simulator and automatically enters this information into the ports list. See Get Signal Information from HDL Simulator for a detailed description of this feature.

  • New — Add a new signal to the list and select it for editing.

  • Delete — Remove a signal from the list.

  • Up — Move the selected signal up one position in the list.

  • Down — Move the selected signal down one position in the list.

To commit edits to the Simulink model, you must also click Apply after selecting parameter values.

    Note:   When you import VHDL signals from the HDL simulator , HDL Verifier returns the signal names in all capitals.

To edit a signal name, double-click on the name. Set the signal properties on the same line and in the associated columns. The properties of a signal are as follows.

Full HDL Name

Specifies the signal path name, using the HDL simulator path name syntax. For example (for use with Incisive®), a path name for an input port might be manchester.samp. The signal can be at any level of the HDL design hierarchy. The HDL Cosimulation block port corresponding to the signal is labeled with the Full HDL Name.

For rules on specifying signal/port and module path specifications in Simulink, see Specify HDL Signal/Port and Module Paths for Cosimulation.

    Copying Signal Path Names   You can copy signal path names directly from the HDL simulator wave window and paste them into the Full HDL Name field, using the standard copy and paste commands in the HDL simulator and Simulink. You must use the Path.Name view and not Db::Path.Name view. After pasting a signal path name into the Full HDL Name field, you must click the Apply button to complete the paste operation and update the signal list.

I/O Mode

Select either Input, Output, or both.

Input designates signals of your HDL module that Simulink will drive. Simulink deposits values on the specified the HDL simulator signal at the signal's sample rate.

    Note:   When you define a block input port, make sure that only one source is set up to drive input to that signal. For example, you should avoid defining an input port that has multiple instances. If multiple sources drive input to a single signal, your simulation model may produce unexpected results.

Output designates signals of your HDL module that Simulink will read. For output signals, you must specify an explicit sample time. You can also specify any data type (except width). For details on specifying a data type, see Date Type and Fraction Length in a following section.

Because Simulink signals do not have the semantic of tri-states (there is no 'Z' value), you will gain no benefit by connecting to a bidirectional HDL signal directly. To interface with bidirectional signals, you can first interface to the input of the output driver, then the enable of the output driver and the output of the input driver. This approach leaves the actual tri-state buffer in HDL where resolution functions can handle interfacing with other tri-state buffers.

Sample Time

This property becomes available only when you specify an output signal. You must specify an explicit sample time.

Sample Time represents the time interval between consecutive samples applied to the output port. The default sample time is 1. The exact interpretation of the output port sample time depends on the settings of the Timescales pane of the HDL Cosimulation block. See also Simulation Timescales.

Data Type, Fraction Length

These two related parameters apply only to output signals.

The Data Type property is enabled only for output signals. You can direct Simulink to determine the data type, or you can assign an explicit data type (with option fraction length). By explicitly assigning a data type, you can force fixed-point data types on output ports of an HDL Cosimulation block.

The Fraction Length property specifies the size, in bits, of the fractional part of the signal in fixed-point representation. Fraction Length becomes available if you do not set the Data Type property to Inherit.

The data type specification for an output port depends on the signal width and by the Data Type and Fraction Length properties of the signal.

    Note:   The Data Type and Fraction Length properties apply only to the following signals:

    • VHDL signals of any logic type, such as STD_LOGIC or STD_LOGIC_VECTOR

    • Verilog signals of wire or reg type

To assign a port data type, set the Data Type and Fraction Length properties as follows:

  • Select Inherit from the Data Type list if you want Simulink to determine the data type.

    This property defaults to Inherit. When you select Inherit, the Fraction Length edit field becomes unavailable.

    Simulink always double checks that the word-length back propagated by Simulink matches the word length queried from the HDL simulator. If they do not match, Simulink generates an error message. For example, if you connect a Signal Specification block to an output, Simulink will force the data type specified by Signal Specification block on the output port.

    If Simulink cannot determine the data type of the signal connected to the output port, it will query the HDL simulator for the data type of the port. As an example, if the HDL simulator returns the VHDL data type STD_LOGIC_VECTOR for a signal of size N bits, the data type ufixN is forced on the output port. (The implicit fraction length is 0.)

  • Select Signed from the Data Type list if you want to explicitly assign a signed fixed point data type. When you select Signed, the Fraction Length edit field becomes available. HDL Verifier assigns the port a fixed-point type sfixN_EnF, where N is the signal width and F is the Fraction Length.

    For example, if you specify Data Type as Signed and a Fraction Length of 5 for a 16-bit signal, Simulink forces the data type to sfix16_En5. For the same signal with a Data Type set to Signed and Fraction Length of -5, Simulink forces the data type to sfix16_E5.

  • Select Unsigned from the Data Type list if you want to explicitly assign an unsigned fixed point data type When you select Unsigned, the Fraction Length edit field becomes available. HDL Verifier assigns the port a fixed-point type ufixN_EnF, where N is the signal width and F is the Fraction Length.

    For example, if you specify Data Type as Unsigned and a Fraction Length of 5 for a 16-bit signal, Simulink forces the data type to ufix16_En5. For the same signal with a Data Type set to Unsigned and Fraction Length of -5 , Simulink forces the data type to ufix16_E5.

Connection Pane

This figure shows the default configuration of the Connection pane (example shown is for use with Incisive). The block defaults to a shared memory configuration for communication between Simulink and the HDL simulator, when they run on a single computer.

If you select TCP/IP socket mode communication, the pane displays additional properties, as shown in the following figure.

Connection Mode

If you want to bypass the HDL simulator when you run a Simulink simulation, use these options to specify what type of simulation connection you want. Select one of the following options:

  • Full Simulation: Confirm interface and run HDL simulation (default).

  • Confirm Interface Only: Connect to the HDL simulator and check for signal names, dimensions, and data types, but do not run HDL simulation.

  • No Connection: Do not communicate with the HDL simulator. The HDL simulator does not need to be started.

With the second and third options, the HDL Verifier cosimulation interface does not communicate with the HDL simulator during Simulink simulation.

The HDL Simulator is running on this computer

Select this option if you want to run Simulink and the HDL simulator on the same computer. When both applications run on the same computer, you have the choice of using shared memory or TCP sockets for the communication channel between the two applications. If you do not select this option, only TCP/IP socket mode is available, and the Connection method list becomes unavailable.

Connection method

This list becomes available when you select The HDL Simulator is running on this computer. Select Socket if you want Simulink and the HDL simulator to communicate via a designated TCP/IP socket. Select Shared memory if you want Simulink and the HDL simulator to communicate via shared memory. For more information on these connection methods, see Communications for HDL Cosimulation.

Host name

If you run Simulink and the HDL simulator on different computers, this text field becomes available. The field specifies the host name of the computer that is running your HDL simulation in the HDL simulator.

Port number or service

Indicate a valid TCP socket port number or service for your computer system (if not using shared memory). For information on choosing TCP socket ports, see TCP/IP Socket Ports.

Show connection info on icon

When you select this option, Simulink indicates information about the selected communication method and (if applicable) communication options information on the HDL Cosimulation block icon. If you select shared memory, the icon displays the string SharedMem. If you select TCP socket communication, the icon displays the string Socket and displays the host name and port number in the format hostname:port.

In a model that has multiple HDL Cosimulation blocks, with each communicating to different instances of the HDL simulator in different modes, this information helps to distinguish between different cosimulation sessions.

Timescales Pane

The Timescales pane of the HDL Cosimulation block parameters dialog box lets you choose a timing relationship between Simulink and the HDL simulator, either manually or automatically. The following figure shows the default settings of the Timescales pane (example shown for use with ModelSim).

The Timescales pane specifies a correspondence between one second of Simulink time and some quantity of HDL simulator time. This quantity of HDL simulator time can be expressed in one of the following ways:

  • Using relative timing mode. HDL Verifier defaults to relative timing mode.

  • Using absolute timing mode

For more information on calculating relative and absolute timing modes, see Defining the Simulink and HDL Simulator Timing Relationship.

For detailed information on the relationship between Simulink and the HDL simulator during cosimulation, and on the operation of relative and absolute timing modes, see Simulation Timescales.

The following sections describe how to specify the timing relationship, either automatically or manually.

Automatically Specifying the Timing Relationship

To have the HDL Verifier software calculate the timing relationship for you, perform the following steps and enter any applicable information in the Timescales pane (as shown in the following figure).

  1. Verify that the HDL simulator is running. HDL Verifier software can obtain the resolution limit of the HDL simulator only when that simulator is running.

  2. Choose whether you want to have HDL Verifier software suggest a timescale at this time or if you want to have the software perform this calculation when the simulation begins in Simulink.

    • To have the calculation performed while you are configuring the block, click the Timescale option, and then click Determine Timescale Now. The software connects Simulink with the HDL simulator so that Simulink can use the HDL simulator resolution to calculate the best timescale. The link then displays those results to you in the Timescale Details dialog box.

        Note:   For the results to display, make sure the HDL simulator is running and the design loaded for cosimulation. The simulation does not have to be running.

      You can accept the timescale the software suggests, or you can make changes in the port list directly:

      • If you want to revert to the originally calculated settings, click Use Suggested Timescale.

      • If you want to view sample times for all ports in the HDL design, select Show all ports and clocks.

    • To have the calculation performed when the simulation begins, select Automatically determine timescale at start of simulation, and click Apply. You obtain the same Timescale Details dialog box when the simulation starts in Simulink.

        Note:   For the results to display, make sure the HDL simulator is running and the design loaded for cosimulation. The simulation does not have to be running.

    HDL Verifier software analyzes all the clock and port signal rates from the HDL Cosimulation block when the software calculates the scale factor.

      Note:   HDL Verifier software cannot automatically calculate a sample timescale based on any signals driven via Tcl commands or in the HDL simulator. The link software cannot perform such calculations because it cannot know the rates of these signals.

    The link software returns the sample rate in either seconds or ticks:

    • If the results are in seconds, then the link software was able to resolve the timing differences in favor of fidelity (absolute time).

    • If the results are in ticks, then the link software was best able to resolve the timing differences in favor of efficiency (relative time).

    Each time you select Determine Timescale Now or Automatically determine timescale at start of simulation, the HDL Verifier software opens an interactive display. This display explains the results of the timescale calculations. If the link software cannot calculate a timescale for the given sample times, adjust your sample times in the Port List.

  3. Click Apply to commit your changes.

    Note:   HDL Verifier does not support timescales calculated automatically from frame-based signals.

For more on the timing relationship between the HDL simulator and Simulink, see Simulation Timescales.

Manually Specifying a Relative Timing Relationship

To manually configure relative timing mode for a cosimulation, perform the following steps:

  1. Select the Timescales tab of the HDL Cosimulation block parameters dialog box.

  2. Verify that Tick, the default setting, is selected. If it is not, then select it from the list on the right.

  3. Enter a scale factor in the text box on the left. The default scale factor is 1. For example, the next figure, shows the Timescales pane configured for a relative timing correspondence of 10 HDL simulator ticks to 1 Simulink second.

  4. Click Apply to commit your changes.

Manually Specifying an Absolute Timing Relationship

To manually configure absolute timing mode for a cosimulation, perform the following steps:

  1. Select the Timescales tab of the HDL Cosimulation block parameters dialog box.

  2. Select a unit of absolute time from the list on the right. The units available include fs (femtoseconds), ps (picoseconds), ns (nanoseconds), us (microseconds), ms (milliseconds), and s (seconds).

  3. Enter a scale factor in the text box on the left. The default scale factor is 1. For example, in the next figure, the Timescales pane is configured for an absolute timing correspondence of 1 HDL simulator second to 1 Simulink second.

  4. Click Apply to commit your changes.

Clocks Pane

You can create optional rising-edge and falling-edge clocks that apply stimuli to your cosimulation model. To do so, use the Clocks pane of the HDL Cosimulation block.

The scrolling list at the center of the pane displays HDL clocks that drive values to the HDL signals that you are modeling, using the deposit method.

Maintain the list of clock signals with the buttons on the left of the pane:

  • New — Add a new clock signal to the list and select it for editing.

  • Delete — Remove a clock signal from the list.

  • Up — Move the selected clock signal up one position in the list.

  • Down — Move the selected clock signal down one position in the list.

To commit edits to the Simulink model, you must also click Apply.

A clock signal has the following properties.

Full HDL Name

Specify each clock as a signal path name, using the HDL simulator path name syntax. For example: /manchester/clk or manchester.clk.

For information about and requirements for path specifications in Simulink, see Specify HDL Signal/Port and Module Paths for Cosimulation.

    Note:   You can copy signal path names directly from the HDL simulator wave window and paste them into the Full HDL Name field, using the standard copy and paste commands in the HDL simulator and Simulink. You must use the Path.Name view and not Db::Path.Name view. After pasting a signal path name into the Full HDL Name field, you must click the Apply button to complete the paste operation and update the signal list.

Edge

Select Rising or Falling to specify either a rising-edge clock or a falling-edge clock.

Period

You must either specify the clock period explicitly or accept the default period of 2.

If you specify an explicit clock period, you must enter a sample time equal to or greater than 2 resolution units (ticks).

If the clock period (whether explicitly specified or defaulted) is not an even integer, Simulink cannot create a 50% duty cycle. Instead, the HDL Verifier software creates the falling edge at

clockperiod/2

(rounded down to the nearest integer).

    Note:   The Clocks pane does not support vectored signals. Signals must be logic types with 1 and 0 values.

For instructions on adding and editing clock signals, see Creating Optional Clocks with the Clocks Pane of the HDL Cosimulation Block.

Simulation Pane

Specify tools command language (Tcl) commands to be executed before and after the HDL simulator simulates the HDL component of your Simulink model (example shown for use with ModelSim).

You may specify any valid Tcl command string. The Tcl command string you specify cannot include commands that load an HDL simulator project or modify simulator state. For example, the string cannot include commands such as start, stop, or restart (for ModelSim) or run, stop, or reset (for Incisive).

Time to run HDL simulator before cosimulation starts:

Specifies the amount of time to run the HDL simulator before beginning simulation in Simulink. Specifying this time properly aligns the signal of the Simulink block and the HDL signal so that they can be compared and verified directly without additional delays.

This setting consists of a PreRunTime value and a PreRunTimeUnit value.

  • PreRunTime: Any valid time value. The default is 0.

  • PreRunTimeUnit: Specifies the units of time for PreRunTime. You can select one of:

    • Tick

    • s

    • ms

    • us

    • ns

    • ps

    • fs

This parameter allows HDL Verifier properly align the signal of your behavioral block and the HDL signal so that they can be compared and verified directly without additional delays.

Pre-simulation commands

Contains Tcl commands to be executed before the HDL simulator simulates the HDL component of your Simulink model. You can specify one Tcl command per line in the text box or enter multiple commands per line by appending each command with a semicolon (;), the standard Tcl concatenation operator.

Use of this field can range from something as simple as a one-line echo command to confirm that a simulation is running to a complex script that performs an extensive simulation initialization and startup sequence.

Post-simulation commands

Contains Tcl commands to be executed after the HDL simulator simulates the HDL component of your Simulink model. You can specify one Tcl command per line in the text box or enter multiple commands per line by appending each command with a semicolon (;), the standard Tcl concatenation operator.

    Note for ModelSim Users   After each simulation, it takes ModelSim time to update the coverage result. To prevent the potential conflict between this process and the next cosimulation session, add a short pause between each successive simulation.

Creating a Tcl Script as an Alternative to Using the Simulation Pane

You can create a Tcl script that lists the Tcl commands you want to execute on the HDL simulator, either pre- or post-simulation.

 Tcl Scripts for ModelSim Users

 Tcl Scripts for Incisive Users

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