Documentation

hdlverifier.FILSimulation System object

Package: hdlverifier

Construct System object for FIL simulation with MATLAB

Description

The FILSimulation System object™ creates, launches, and controls FPGA execution from MATLAB®.

    Note:   Starting in R2016b, instead of using the step method to perform the operation defined by the System object, you can call the object with arguments, as if it were a function. For example, y = step(obj,x) and y = obj(x) perform equivalent operations.

Construction

hdlverifier.FILSimulation is a virtual class and cannot be instantiated directly. To use it, launch the FPGA-in-the-Loop Wizard and generate your own custom FILSimulation derived class. Then you can instantiate your own FIL simulation object with the following function:

filobj = toplevel_fil creates a new instance of the derived class generated by the FPGA-in-the-Loop Wizard. toplevel is the name of the top-level module in your HDL code.

You can adjust writable properties on the System object by using the get and set methods or by setting the property directly. See Properties.

Properties

Connection

Parameters for the connection with the FPGA board

R/W Access: Read only

Default: char('UDP','192.168.0.2','00-0A-35-02-21-8A')

Attributes:

Connection typecharacter vectorExample: 'UDP'
Board IP addresscharacter vectorExample: '192.168.0.2'
Board MAC address (optional)character vectorExample: '00-0A-35-02-21-8A'

DUTName

DUT top level name

R/W Access: Read only

Default: ''

Attributes:

Name of DUT top levelcharacter vectorExample: 'inverter_top'

FPGABoard

FPGA board name

R/W Access: Read only

Default: ''

FPGAProgrammingFile

Path to the programming file for the FPGA

R/W Access: Read and write

Default: ''

Attributes:

Path namecharacter vectorExample: 'c:\work\filename'

FPGAVendor

Name of the FPGA chip vendor

R/W Access: Read only

Default: 'Xilinx'

Attributes:

Chip vendor namecharacter vectorExamples: 'Altera', 'Xilinx'

InputBitWidths

Input widths, in bits

R/W Access: Read only

Default: 0

Attributes:

Integer or vector of integer specifying the bit widths of the inputs.
If you provide only a scalar, the inputs each have the same bit width; otherwise you should provide a vector of the same size as the number of inputs.

integer or vector of integersExamples:
10
[12,6]

InputSignals

Input paths in the HDL code

R/W Access: Read only

Default: ''

Attributes:

input port name of each input in the HDLcharacter vector or cell array of N character vectorsExamples: 'in1', char('in1','in2')

OutputBitWidths

Output widths, in bits

R/W Access: Read only

Default: 0

Attributes:

Integer or vector of integer specifying the bit widths of the outputs.
If you provide only a scalar, the outputs each have the same bit width. Otherwise you should provide a vector of the same size as the number of outputs.
integer or vector of integersExamples:
10
[12,6]

OutputDataTypes

Output data types

R/W Access: Read and write

Default: fixedpoint

Attributes:

Character vector or cell array of N character vectors specifying the data type of the output.
If you only provide one data type, each of the outputs has the same type. Otherwise, you should provide a cell array of the same size as the number of outputs.
character vector or cell array of N character vectorsExamples: 'logical', 'integer', 'fixedpoint'
char(‘integer','fixedpoint')

OutputDownsampling

Downsampling factor and phase of the outputs

R/W Access: Read and write

Default: [1,0]

Attributes:

Vector of 2 integers: The first integer specifies the downsampling factor and is positive. The second integer specifies the phase and is null or positive and inferior to the downsampling factor.vectorExamples:
[3,1]

OutputFractionLengths

Output fraction lengths

R/W Access: Read and write

Default: 0

Attributes:

Integer or vector of integer specifying the fraction length of the outputs.
If you provide only a scalar, each output has the same fraction length. Otherwise you should provide a vector of the same size as the number of outputs.
integer or vector of integersExamples:
10
[12,6]

OutputSignals

Output port name in the HDL top level

R/W Access: Read only

Default: ''

Attributes:

Character vector or cell array of N character vectors containing the output port name of each output in HDL.character vector or cell array of N character vectorsExamples: 'out1', char('out1','out2')

OutputSigned

Sign of the outputs

R/W Access: Read and write

Default: false

Attributes:

Boolean or vector of boolean specifying the sign of the outputs.
If you provide only a scalar, each output has the same sign. Otherwise, you should provide a vector of the same size as the number of outputs.
Boolean of vector of Boolean Examples: true (signed), false (unsigned)
[true, true, false]

OverclockingFactor

Hardware overclocking factor

R/W Access: Read and write

Default: 1

Attributes:

Positive integer specifying the overclocking factor for the hardware.integerExample:
3

ScanChainPosition

Position of the FPGA in the JTAG scan chain

R/W Access: Read only

Default: 1

Attributes:

Positive integer specifying the position of the FPGA in the JTAG scan chain.integerExample:
1

SourceFrameSize

Frame size of the source (only for HDL source block)

R/W Access: Read and write

Default: 1

Attributes:

Integer specifying the frame size of the source when the HDL is a source block (no input).integerExample:
1

Methods

cloneCreate FILSimulation object with same property values
isLockedSystem object locked status for input attributes and nontunable properties
programFPGALoad programming file onto FPGA
releaseRelease connection to FPGA board and allow changes to object
stepRun FIL simulation for set of inputs and return output
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