Class: hdlverifier.FILSimulation
Package: hdlverifier

Run FIL simulation for set of inputs and return output


[hdloutputs] = step(filobj,[hdlinputs])


[hdloutputs] = step(filobj,[hdlinputs]) connects to the FPGA, writes hdlinputs to the FPGA and reads hdloutputs from the FPGA.

    Note:   H specifies the System object™ on which to run this step method.

    The object performs an initialization the first time the step method is executed. This initialization locks nontunable properties and input specifications, such as dimensions, complexity, and data type of the input data. If you change a nontunable property or an input specification, the System object issues an error. To change nontunable properties or inputs, you must first call the release method to unlock the object.

Input Arguments


Instance of FILSimulation


Set of inputs to run on FPGA

Output Arguments


Set of outputs returned by the FPGA

Was this topic helpful?