Documentation

step

System object: hdlverifier.FILSimulation
Package: hdlverifier

Run FIL simulation for set of inputs and return output

Syntax

[hdloutputs] = step(filobj,[hdlinputs])

Description

    Note:   Starting in R2016b, instead of using the step method to perform the operation defined by the System object™, you can call the object with arguments, as if it were a function. For example, y = step(obj,x) and y = obj(x) perform equivalent operations.

[hdloutputs] = step(filobj,[hdlinputs]) connects to the FPGA, writes hdlinputs to the FPGA and reads hdloutputs from the FPGA.

    Note:   H specifies the System object on which to run this step method.

    The object performs an initialization the first time the step method is executed. This initialization locks nontunable properties and input specifications, such as dimensions, complexity, and data type of the input data. If you change a nontunable property or an input specification, the System object issues an error. To change nontunable properties or inputs, you must first call the release method to unlock the object.

Input Arguments

filobj

Instance of FILSimulation

hdlinputs

Set of inputs to run on FPGA

Output Arguments

hdloutputs

Set of outputs returned by the FPGA

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