Generate value change dump (VCD) file
HDL Verifier / For Use with Mentor Graphics Modelsim
HDL Verifier / For Use with Cadence Incisive
The To VCD File block generates a VCD file that logs changes to its input ports. You can use VCD files during design verification in the following ways:
For comparing results of multiple simulation runs, using the same or different simulator environments
As input to post-simulation analysis tools
For porting areas of an existing design to a new design
You can specify the following parameters:
The file name to be used for the generated file
The number of block input ports that are to receive signal data
The timescale to relate Simulink® sample times with HDL simulator ticks
VCD files can grow large for larger designs or smaller designs with longer simulation runs. The maximum number of signals supported in a VCD file generated by the To VCD File block is 943 (830,584).
You can use the To VCD File block in models running in Normal, Accelerator, or Rapid Accelerator simulation modes. The To VCD File parameters are not tunable in any of the simulation modes. For more information about these modes, see How Acceleration Modes Work (Simulink).
Note: The To VCD File block does not support framed signals.
The To VCD File block is integrated into the Simulink Signal
& Scope Manager. When you add a VCD block via the Signal &
Scope manager, the signal name that appears in the VCD file may not
be the one you specified. After simulation, open the VCD file and
check the signal name. If you cannot find the signal name you specified,
look for an automatic signal name like
The format of generated VCD files adheres to IEEE® Std 1364-2001. The following table describes the format.
Generated VCD File Format
$date 23-Sep-2003 14:38:11 $end
|Date and time the file was generated.|
$version HDL Verifier version 1.0 $ end
|Version of the VCD block that generated the file.|
$timescale 1 ns $ end
|The time scale that was used during the simulation.|
$scope module manchestermodel $end
|The scope of the module being dumped.|
$var wire 1 ! Original Data  $end $var wire 1 " Recovered Clock  $end $var wire 1 # Recovered Data  $end $var wire 1 $ Data Validity  $end
Variable definitions. Each definition associates a signal with character identification code (symbol).
symbols are derived from printable characters in the ASCII character
Variable definitions also include the variable type (wire) and size in bits.
|Marks a change to the next higher level in the HDL design hierarchy.|
|Marks the end of the header and definitions section.|
|Simulation start time.|
$dumpvars 0! 0" 0# 0$ $end
|Lists the values of all defined variables at time equals 0.|
The starting point of logged value changes from checks of variable values made at each simulation time increment.
entry indicates that at 63 nanoseconds, the value of signal
. . . #1160 1# 1$
|At 116 nanoseconds the values of signals |
$dumpoff x! x" x# x$ $end
|Marks the end of the file by dumping the values
of all variables as the value |
You can graphically display VCD file data or analyze the data
with postprocessing tools. For example, the ModelSim®
converts a VCD file to a
WLF file that you can
view in a ModelSim wave window. Other examples
of postprocessing include the extraction of data pertaining to a particular
section of a design hierarchy or data generated during a specific
The block has a number of input ports that represent signals to log to the VCD file. It has no output ports.
VCD file name— Generated VCD file
The name of the generated VCD file. If you specify a file name only, Simulink places the file in your current MATLAB® folder. Specify a complete path name to place the generated file in a different location. If you specify the same name for multiple To VCD File blocks, Simulink automatically adds a numeric postfix to identify each instance uniquely.
If you want the generated file to have a
Number of input ports— Input signals to log
Number of input ports that the block collects signal data from. The block can log up to 943 (830,584) signals, each of which maps to a unique symbol in the VCD file.
In some cases, a single input port maps to multiple signals (and symbols). This multiple mapping occurs when the input port receives a multidimensional signal. Because the VCD specification does not include multidimensional signals, Simulink flattens them to a 1-D vector in the file.
Timescale— Timing relationship between Simulink and the HDL simulator
Correspondence between one second of Simulink time and some quantity of HDL simulator time. You can express this quantity of HDL simulator time in one of the following ways:
In relative terms (i.e., as some number of HDL simulator ticks). In this case, the cosimulation operates in relative timing mode, which is the timing mode default.
To use relative mode, select
the pop-up list at the label in the HDL simulator,
and enter the desired number of ticks in the edit box at 1
second in Simulink corresponds to. The default value is
In absolute units (such as milliseconds or nanoseconds). In this case, the cosimulation operates in absolute timing mode.
To use absolute mode, select the desired resolution unit from
the pop-up list at the label in the HDL simulator (available
and enter the desired number of resolution units in the edit box at 1
second in Simulink corresponds to. Then, set the value
of the HDL simulator tick by selecting
100 from the pop-up list at 1
HDL Tick is defined as and the resolution unit from the
pop-up list at defined as.