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Simulink Cosimulation

HDL cosimulation with Simulink®

Blocks

HDL Cosimulation Cosimulate hardware component by communicating with HDL module instance executing in HDL simulator
To VCD File Generate value change dump (VCD) file

Apps

Cosimulation Wizard Generate a cosimulation block or System object from existing HDL files

Functions

hdlsimulink Load instantiated HDL design for cosimulation with Cadence Incisive and Simulink
nclaunch Start and configure Cadence Incisive simulators for use with HDL Verifier software
vsim Start and configure ModelSim for use with HDL Verifier
vsimulink Load instantiated HDL module for cosimulation with ModelSim and Simulink
breakHdlSim Execute stop command in HDL simulator from MATLAB
nomatlabtb End active MATLAB test bench and MATLAB component sessions
notifyMatlabServer Send HDL simulator event and process IDs to MATLAB server
pingHdlSim Block cosimulation until HDL simulator is ready for simulation
tclHdlSim Execute Tcl command in Incisive or ModelSim simulator
waitForHdlClient Wait until specified event ID is obtained or time-out occurs
dec2mvl Convert decimal integer to binary character vector
mvl2dec Convert multivalued logic to decimal

Topics

Startup and Connection

Startup for HDL Cosimulation

Get the requirements for machine configurations when using HDL Verifier™ with MATLAB® and Simulink.

Supported EDA Tools and Hardware

List of supported third-party EDA software and FPGA boards.

Start HDL Simulator for Cosimulation in Simulink

Set up the connection between the HDL simulator and Simulink.

TCP/IP Socket Ports

Provides some direction for choosing TCP/IP socket ports

Cross-Network Cosimulation

Provides instructions for performing cosimulation across a local network

Test Bench

Simulink as a Test Bench

Provides an introduction to the process for integrating HDL Verifier blocks into a Simulink design.

Create a Simulink Cosimulation Test Bench

The steps to code and run a Simulink-as-test bench cosimulation for use with the HDL Verifier software.

Verify HDL Module with Simulink Test Bench

The steps for setting up an HDL Verifier session that uses Simulink to verify a simple VHDL® model.

Verify Raised Cosine Filter Design Using Simulink

Provides instruction in using the Cosimulation Wizard to create a Simulink model for cosimulation

Verification of Generated HDL Code with Cosimulation Test Bench (requires HDL Coder license)

Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)

How to generate test bench and code coverage for your HDL code using the HDL Workflow Advisor

Test Bench Automatic Verification with Simulink

The automatic verification feature integrates verification as part of the workflow for HDL Cosimulation using the HDL Workflow Advisor.

Component Algorithm

Component Simulation with Simulink

Provides an introduction to the process for integrating blocks into a Simulink design.

Create Simulink Model for Component Cosimulation

Provides a high-level view of the steps involved in coding and running a Simulink-as-component cosimulation for use with the software.

Cosimulation with Simulink

HDL Cosimulation

The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.

Performing Cosimulation

Next steps after you generate a function or block representing your HDL module.

Import HDL Code for Cosimulation

Prepare for cosimulation and choose whether to cosimulate your HDL code as a function, System object, or block.

Import HDL Code for HDL Cosimulation Block

Generate a Simulink block to cosimulate your HDL code.

Run a Simulink Cosimulation Session

Run your test bench or algorithm, including the cosimulation of your HDL module.

HDL Simulator Concepts

Simulation Timescales

The representation of simulation time differs significantly between the HDL simulator and Simulink.

Clock, Reset, and Enable Signals

You can create rising-edge or falling-edge clocks, resets, or clock enable signals that apply internal stimuli to your model under cosimulation.

Simulation Speed Improvement Tips

Provides suggestions for optimizing your cosimulation performance

Data Type Conversions

If your HDL application needs to send HDL data to a MATLAB function, you may first need to convert the data to a type supported by MATLAB and the HDL Verifier software.

Race Conditions in HDL Simulators

Describes ways to avoid race conditions in hardware cosimulations with MATLAB and Simulink software

Recording Signal State Transitions for Post-Processing

Add a Value Change Dump (VCD) File

A value change dump (VCD) file logs changes to variable values, such as the values of signals, in a file during a simulation session.

Visually Compare Simulink Signals with HDL Signals

Guides you through the basic steps for adding a To VCD File block to a Simulink model for use with cosimulation

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