Create Xilinx KC705 Evaluation Board Definition File


For FPGA-in-the-loop, you can use your own qualified FPGA board, even if it is not in the pre-registered FPGA board list supplied by MathWorks®. Using the New FPGA Board wizard, you can create a board definition file that describes your custom FPGA board.

In this example, you can follow the workflow of creating a board definition file for the Xilinx® KC705 evaluation board to use with FIL simulation.

What You Need to Know Before Starting

  • Check the board specification so that you have the following information ready:

    • FPGA interface to the Ethernet PHY chip

    • Clock pins names and numbers

    • Reset pins names and numbers

    In this example, the required information is supplied to you. In general, you can find this type of information in the board specification file. This example uses the KC705 Evaluation Board for the Kintex-7 FPGA User Guide, published by Xilinx.

  • For validation, you must have Xilinx or Altera® on your path. Use the hdlsetuptoolpath function to configure the tool for use with MATLAB®.

  • To verify programming the FPGA board after you add its definition file, attach the custom board to your computer. However, having the board connected is not necessary for creating the board definition file.

Start New FPGA Board Wizard

  1. Start the FPGA Board Manager by entering the following command at the MATLAB prompt:

  2. Click Create Custom Board to open the New FPGA Board wizard.

Provide Basic Board Information

  1. In the Basic Information pane, enter the following information:

    • Board Name: Enter "My Xilinx KC705 Board"

    • Vendor: Select Xilinx

    • Family: Select Kintex7

    • Device: Select xc7k325t

    • Package: Select ffg900

    • Speed: Select -2

    • JTAG Chain Position: Select 1

    The information you just entered can be found in the KC705 Evaluation Board for the Kintex-7 FPGA User Guide.

  2. Click Next.

Specify FPGA Interface Information

  1. In the Interfaces pane, perform the following tasks.

    1. Select FIL Interface. This option is required for using your board with FPGA-in-the-loop.

    2. Select GMII in the PHY Interface Type. This option indicates that the onboard FPGA is connected to the Ethernet PHY chip via a GMII interface.

    3. Leave the User-defined I/O option in the FPGA Turnkey Interface section cleared. FPGA Turnkey workflow is not the focus of this example.

    4. Clock Frequency: Enter 200. This Xilinx KC705 board has multiple clock sources. The 200 MHz clock is one of the recommended clock frequencies for use with Ethernet interface (50, 100, 125, and 200 MHz).

    5. Clock Type: Select Differential.

    6. Clock_P Pin Number: Enter AD12.

    7. Clock_N Pin Number: Enter AD11.

    8. Clock IO Standard — Leave blank.

    9. Reset Pin Number: Enter AB7. This value supplies a global reset to the FPGA.

    10. Active Level: Select Active-High.

    11. Reset IO Standard — Leave blank.

    You can obtain all necessary information from the board design specification.

  2. Click Next.

Enter FPGA Pin Numbers

  1. In the FILI/O pane, enter the numbers for each FPGA pin. This information is required.

    Pin numbers for RXD and TXD signals are entered from the least significant digit (LSD) to the most significant digit (MSB), separated by a comma.

    For signal name...Enter FPGA pin number...

  2. Click Advanced Options to expand the section.

  3. Check the Generate MDIO module to override PHY settings option.

    This option is selected for the following reasons:

    • There are jumpers on the Xilinx KC705 board that configure the Ethernet PHY device to MII, GMII, RGMII, or SGMII mode. Since this example uses the GMII interfaces, the FPGA board does not work if the PHY devices are set to the wrong mode. When the Generate MDIO module to override PHY settings option is selected, the FPGA uses the Management Data Input/Output (MDIO) bus to override the jumper settings and configure the PHY chip to the correct GMII mode.

    • This option currently only applies to Marvell Alaska PHY device 88E1111 and this KC705 board is using the Marvel device.

  4. PHY address (0 – 31): Enter 7.

  5. Click Next.

Run Optional Validation Tests

This step provides a validation test for you to verify if the entered information is correct by performing FPGA-in-the-loop cosimulation. You need Xilinx ISE 13.4 or higher versions installed on the same computer. This step is optional and you can skip it, if you prefer.

    Note:   For validation, you must have Xilinx or Altera on your path. Use the hdlsetuptoolpath function to configure the tool for use with MATLAB.

To run this test, perform the following actions.

  1. Check the Run FPGA-in-the-Loop test option.

  2. If you have the board attached, check the Include FPGA board in the test option. You need to supply the IP address of the FPGA Board. This example assumes that the Xilinx KC705 board is attached to your host computer and it has an IP address of

  3. Click Run Selected Test(s). The tests take about 10 minutes to complete.

Save Board Definition File

  1. Click Finish to exit the New FPGA Board wizard. A Save As dialog box pops up and asks for the location of the FPGA board definition file. For this example, save as C:\boardfiles\KC705.xml.

  2. Click Save to save the file and exit.

Use New FPGA Board

  1. After you save the board definition file, you are returned to the FPGA Board Manager. In the FPGA Board List, you can now see the new board you defined.

    Click OK to close the FPGA Board Manager.

  2. You can view the new board in the board list from either the FIL wizard or the HDL Workflow Advisor.

    1. Start the FIL wizard from the MATLAB prompt.


      The Xilinx KC705 board appears in the board list and you can select it for FPGA-in-the-loop simulation.

    2. Start HDL Workflow Advisor.

      In step 1.1, select FPGA-in-the-Loop and click Launch Board Manager.

      The Xilinx KC705 board appears in the board list and you can select it for FPGA-in-the-loop simulation.

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